Patents by Inventor Akihiro Ishizuka

Akihiro Ishizuka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150171195
    Abstract: A semiconductor device having a transistor including an oxide semiconductor film is disclosed. In the semiconductor device, the oxide semiconductor film is provided along a trench formed in an insulating layer. The trench includes a lower end corner portion and an upper end corner portion having a curved shape with a curvature radius of longer than or equal to 20 nm and shorter than or equal to 60 nm, and the oxide semiconductor film is provided in contact with a bottom surface, the lower end corner portion, the upper end corner portion, and an inner wall surface of the trench. The oxide semiconductor film includes a crystal having a c-axis substantially perpendicular to a surface at least over the upper end corner portion.
    Type: Application
    Filed: December 19, 2014
    Publication date: June 18, 2015
    Inventors: Atsuo ISOBE, Toshinari SASAKI, Shinya SASAGAWA, Akihiro ISHIZUKA
  • Patent number: 9006803
    Abstract: An insulating layer is provided with a projecting structural body, and a channel formation region of an oxide semiconductor layer is provided in contact with the projecting structural body, whereby the channel formation region is extended in a three dimensional direction (a direction perpendicular to a substrate). Thus, it is possible to miniaturize a transistor and to extend an effective channel length of the transistor. Further, an upper end corner portion of the projecting structural body, where a top surface and a side surface of the projecting structural body intersect with each other, is curved, and the oxide semiconductor layer is formed to include a crystal having a c-axis perpendicular to the curved surface.
    Type: Grant
    Filed: April 13, 2012
    Date of Patent: April 14, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Atsuo Isobe, Toshinari Sasaki, Shinya Sasagawa, Akihiro Ishizuka
  • Publication number: 20150093855
    Abstract: To provide a miniaturized semiconductor device with stable electric characteristics in which a short-channel effect is suppressed. Further, to provide a manufacturing method of the semiconductor device. The semiconductor device (transistor) including a trench formed in an oxide insulating layer, an oxide semiconductor film formed along the trench, a source electrode and a drain electrode which are in contact with the oxide semiconductor film, a gate insulating layer over the oxide semiconductor film, a gate electrode over the gate insulating layer is provided. The lower corner portions of the trench are curved, and the side portions of the trench have side surfaces substantially perpendicular to the top surface of the oxide insulating layer. Further, the width between the upper ends of the trench is greater than or equal to 1 time and less than or equal to 1.5 times the width between the side surfaces of the trench.
    Type: Application
    Filed: December 11, 2014
    Publication date: April 2, 2015
    Inventors: Akihiro ISHIZUKA, Shinya SASAGAWA
  • Publication number: 20150084049
    Abstract: An object is to provide a method for manufacturing a semiconductor device including an oxide semiconductor and having improved electric characteristics. The semiconductor device includes an oxide semiconductor film, a gate electrode overlapping the oxide semiconductor film, and a source electrode and a drain electrode electrically connected to the oxide semiconductor film. The method includes the steps of forming a first insulating film including gallium oxide over and in contact with the oxide semiconductor film; forming a second insulating film over and in contact with the first insulating film; forming a resist mask over the second insulating film; forming a contact hole by performing dry etching on the first insulating film and the second insulating film; removing the resist mask by ashing using oxygen plasma; and forming a wiring electrically connected to at least one of the gate electrode, the source electrode, and the drain electrode through the contact hole.
    Type: Application
    Filed: December 3, 2014
    Publication date: March 26, 2015
    Inventors: Akihiro ISHIZUKA, Yutaka YONEMITSU, Shinya SASAGAWA
  • Patent number: 8969144
    Abstract: Described is a method for manufacturing a semiconductor device. A mask is formed over an insulating film and the mask is reduced in size. An insulating film having a projection is formed using the mask reduced in size, and a transistor whose channel length is reduced is formed using the insulating film having a projection. Further, in manufacturing the transistor, a planarization process is performed on a surface of a gate insulating film which overlaps with a top surface of a fine projection. Thus, the transistor can operate at high speed and the reliability can be improved. In addition, the insulating film is processed into a shape having a projection, whereby a source electrode and a drain electrode can be formed in a self-aligned manner.
    Type: Grant
    Filed: October 24, 2013
    Date of Patent: March 3, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hideomi Suzawa, Shinya Sasagawa, Akihiro Ishizuka
  • Patent number: 8946812
    Abstract: To provide a miniaturized semiconductor device with stable electric characteristics in which a short-channel effect is suppressed. Further, to provide a manufacturing method of the semiconductor device. The semiconductor device (transistor) including a trench formed in an oxide insulating layer, an oxide semiconductor film formed along the trench, a source electrode and a drain electrode which are in contact with the oxide semiconductor film, a gate insulating layer over the oxide semiconductor film, a gate electrode over the gate insulating layer is provided. The lower corner portions of the trench are curved, and the side portions of the trench have side surfaces substantially perpendicular to the top surface of the oxide insulating layer. Further, the width between the upper ends of the trench is greater than or equal to 1 time and less than or equal to 1.5 times the width between the side surfaces of the trench.
    Type: Grant
    Filed: July 10, 2012
    Date of Patent: February 3, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Akihiro Ishizuka, Shinya Sasagawa
  • Patent number: 8932913
    Abstract: To provide a semiconductor device which prevents defects and achieves miniaturization. A projecting portion or a trench (a groove portion) is formed in an insulating layer and a channel formation region of a semiconductor layer is provided in contact with the projecting portion or the trench, so that the channel formation region is extended in a direction perpendicular to a substrate. Thus, miniaturization of the transistor can be achieved and an effective channel length can be extended. In addition, before formation of the semiconductor layer, an upper-end corner portion of the projecting portion or the trench with which the semiconductor layer is in contact is subjected to round chamfering, so that a thin semiconductor layer can be formed with good coverage.
    Type: Grant
    Filed: April 13, 2012
    Date of Patent: January 13, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shinya Sasagawa, Akihiro Ishizuka
  • Patent number: 8916868
    Abstract: A semiconductor device having a transistor including an oxide semiconductor film is disclosed. In the semiconductor device, the oxide semiconductor film is provided along a trench formed in an insulating layer. The trench includes a lower end corner portion and an upper end corner portion having a curved shape with a curvature radius of longer than or equal to 20 nm and shorter than or equal to 60 nm, and the oxide semiconductor film is provided in contact with a bottom surface, the lower end corner portion, the upper end corner portion, and an inner wall surface of the trench. The oxide semiconductor film includes a crystal having a c-axis substantially perpendicular to a surface at least over the upper end corner portion.
    Type: Grant
    Filed: April 13, 2012
    Date of Patent: December 23, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Atsuo Isobe, Toshinari Sasaki, Shinya Sasagawa, Akihiro Ishizuka
  • Patent number: 8906737
    Abstract: An object is to provide a method for manufacturing a semiconductor device including an oxide semiconductor and having improved electric characteristics. The semiconductor device includes an oxide semiconductor film, a gate electrode overlapping the oxide semiconductor film, and a source electrode and a drain electrode electrically connected to the oxide semiconductor film. The method includes the steps of forming a first insulating film including gallium oxide over and in contact with the oxide semiconductor film; forming a second insulating film over and in contact with the first insulating film; forming a resist mask over the second insulating film; forming a contact hole by performing dry etching on the first insulating film and the second insulating film; removing the resist mask by ashing using oxygen plasma; and forming a wiring electrically connected to at least one of the gate electrode, the source electrode, and the drain electrode through the contact hole.
    Type: Grant
    Filed: June 9, 2011
    Date of Patent: December 9, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Akihiro Ishizuka, Yutaka Yonemitsu, Shinya Sasagawa
  • Publication number: 20140127868
    Abstract: A miniaturized transistor is provided with high yield. Further, a semiconductor device which has high on-state characteristics and which is capable of high-speed response and high-speed operation is provided. In the semiconductor device, an oxide semiconductor layer, a gate insulating layer, a gate electrode layer, an insulating layer, a conductive film, and an interlayer insulating layer are stacked in this order. A source electrode layer and a drain electrode layer are formed in a self-aligned manner by cutting the conductive film so that the conductive film over the gate electrode layer and the conductive layer is removed and the conductive film is divided. An electrode layer which is in contact with the oxide semiconductor layer and overlaps with a region in contact with the source electrode layer and the drain electrode layer is provided.
    Type: Application
    Filed: January 9, 2014
    Publication date: May 8, 2014
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Toshihiko SAITO, Atsuo ISOBE, Kazuya HANAOKA, Junichi KOEZUKA, Shinya SASAGAWA, Motomu KURATA, Akihiro ISHIZUKA
  • Patent number: 8703560
    Abstract: The present invention provides a method for manufacturing a highly reliable semiconductor device with a small amount of leakage current. In a method for manufacturing a thin film transistor, etching is conducted using a resist mask to form a back channel portion in the thin film transistor, the resist mask is removed, a part of the back channel is etched to remove etching residue and the like left over the back channel portion, whereby leakage current caused by the residue and the like can be reduced. The etching step of the back channel portion can be conducted by dry etching using non-bias.
    Type: Grant
    Filed: June 24, 2013
    Date of Patent: April 22, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hidekazu Miyairi, Shinya Sasagawa, Akihiro Ishizuka
  • Patent number: 8664118
    Abstract: An object is to provide a semiconductor device having excellent characteristics, in which a channel layer includes an oxide semiconductor with high crystallinity. In addition, a semiconductor device including a base film with improved planarity is provided. CMP treatment is performed on the base film of the transistor and plasma treatment is performed thereon after the CMP treatment, whereby the base film can have a center line average roughness Ra75 of less than 0.1 nm. The oxide semiconductor layer with high crystallinity is formed over the base film having planarity, which is obtained by the combination of the plasma treatment and the CMP treatment, thereby improving the characteristics of the semiconductor device.
    Type: Grant
    Filed: July 2, 2012
    Date of Patent: March 4, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Akihiro Ishizuka, Kazuya Hanaoka, Shinya Sasagawa, Sho Nagamatsu
  • Publication number: 20140051209
    Abstract: Described is a method for manufacturing a semiconductor device. A mask is formed over an insulating film and the mask is reduced in size. An insulating film having a projection is formed using the mask reduced in size, and a transistor whose channel length is reduced is formed using the insulating film having a projection. Further, in manufacturing the transistor, a planarization process is performed on a surface of a gate insulating film which overlaps with a top surface of a fine projection. Thus, the transistor can operate at high speed and the reliability can be improved. In addition, the insulating film is processed into a shape having a projection, whereby a source electrode and a drain electrode can be formed in a self-aligned manner.
    Type: Application
    Filed: October 24, 2013
    Publication date: February 20, 2014
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hideomi SUZAWA, Shinya SASAGAWA, Akihiro ISHIZUKA
  • Patent number: 8637864
    Abstract: A miniaturized transistor is provided with high yield. Further, a semiconductor device which has high on-state characteristics and which is capable of high-speed response and high-speed operation is provided. In the semiconductor device, an oxide semiconductor layer, a gate insulating layer, a gate electrode layer, an insulating layer, a conductive film, and an interlayer insulating layer are stacked in this order. A source electrode layer and a drain electrode layer are formed in a self-aligned manner by cutting the conductive film so that the conductive film over the gate electrode layer and the conductive layer is removed and the conductive film is divided. An electrode layer which is in contact with the oxide semiconductor layer and overlaps with a region in contact with the source electrode layer and the drain electrode layer is provided.
    Type: Grant
    Filed: October 1, 2012
    Date of Patent: January 28, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Toshihiko Saito, Atsuo Isobe, Kazuya Hanaoka, Junichi Koezuka, Shinya Sasagawa, Motomu Kurata, Akihiro Ishizuka
  • Patent number: 8592879
    Abstract: Described is a method for manufacturing a semiconductor device. A mask is formed over an insulating film and the mask is reduced in size. An insulating film having a projection is formed using the mask reduced in size, and a transistor whose channel length is reduced is formed using the insulating film having a projection. Further, in manufacturing the transistor, a planarization process is performed on a surface of a gate insulating film which overlaps with a top surface of a fine projection. Thus, the transistor can operate at high speed and the reliability can be improved. In addition, the insulating film is processed into a shape having a projection, whereby a source electrode and a drain electrode can be formed in a self-aligned manner.
    Type: Grant
    Filed: August 30, 2011
    Date of Patent: November 26, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hideomi Suzawa, Shinya Sasagawa, Akihiro Ishizuka
  • Patent number: 8575608
    Abstract: An embodiment is a thin film transistor which includes a gate electrode layer, a gate insulating layer provided so as to cover the gate electrode layer; a first semiconductor layer entirely overlapped with the gate electrode layer; a second semiconductor layer provided over and in contact with the first semiconductor layer and having a lower carrier mobility than the first semiconductor layer; an impurity semiconductor layer provided in contact with the second semiconductor layer; a sidewall insulating layer provided so as to cover at least a sidewall of the first semiconductor layer; and a source and drain electrode layers provided in contact with at least the impurity semiconductor layer. The second semiconductor layer may consist of parts which are apart from each other over the first semiconductor layer.
    Type: Grant
    Filed: December 20, 2010
    Date of Patent: November 5, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shinya Sasagawa, Akihiro Ishizuka, Shinobu Furukawa, Motomu Kurata
  • Publication number: 20130280867
    Abstract: The present invention provides a method for manufacturing a highly reliable semiconductor device with a small amount of leakage current. In a method for manufacturing a thin film transistor, etching is conducted using a resist mask to form a back channel portion in the thin film transistor, the resist mask is removed, a part of the back channel is etched to remove etching residue and the like left over the back channel portion, whereby leakage current caused by the residue and the like can be reduced. The etching step of the back channel portion can be conducted by dry etching using non-bias.
    Type: Application
    Filed: June 24, 2013
    Publication date: October 24, 2013
    Inventors: Hidekazu MIYAIRI, Shinya SASAGAWA, Akihiro ISHIZUKA
  • Patent number: 8501554
    Abstract: The present invention provides a method for manufacturing a highly reliable semiconductor device with a small amount of leakage current. In a method for manufacturing a thin film transistor, etching is conducted using a resist mask to form a back channel portion in the thin film transistor, the resist mask is removed, a part of the back channel is etched to remove etching residue and the like left over the back channel portion, whereby leakage current caused by the residue and the like can be reduced. The etching step of the back channel portion can be conducted by dry etching using non-bias.
    Type: Grant
    Filed: December 3, 2012
    Date of Patent: August 6, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hidekazu Miyairi, Shinya Sasagawa, Akihiro Ishizuka
  • Publication number: 20130075732
    Abstract: A miniaturized transistor having high electric characteristics is provided with high yield. In a semiconductor device including the transistor, high performance, high reliability, and high productivity are achieved. In a semiconductor device including a transistor in which an oxide semiconductor film, a gate insulating film, and a gate electrode layer on side surfaces of which sidewall insulating layers are provided are stacked in this order, source and drain electrode layers are provided in contact with the oxide semiconductor film and the sidewall insulating layers. In a process for manufacturing the semiconductor device, a conductive film and an interlayer insulating film are stacked to cover the oxide semiconductor film, the sidewall insulating layers, and the gate electrode layer, and the interlayer insulating film and the conductive film over the gate electrode layer are removed by a chemical mechanical polishing method, so that the source and drain electrode layers are formed.
    Type: Application
    Filed: September 6, 2012
    Publication date: March 28, 2013
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Toshihiko SAITO, Atsuo ISOBE, Kazuya HANAOKA, Junichi KOEZUKA, Shinya SASAGAWA, Motomu KURATA, Akihiro ISHIZUKA
  • Publication number: 20130020575
    Abstract: To provide a miniaturized semiconductor device with stable electric characteristics in which a short-channel effect is suppressed. Further, to provide a manufacturing method of the semiconductor device. The semiconductor device (transistor) including a trench formed in an oxide insulating layer, an oxide semiconductor film formed along the trench, a source electrode and a drain electrode which are in contact with the oxide semiconductor film, a gate insulating layer over the oxide semiconductor film, a gate electrode over the gate insulating layer is provided. The lower corner portions of the trench are curved, and the side portions of the trench have side surfaces substantially perpendicular to the top surface of the oxide insulating layer. Further, the width between the upper ends of the trench is greater than or equal to 1 time and less than or equal to 1.5 times the width between the side surfaces of the trench.
    Type: Application
    Filed: July 10, 2012
    Publication date: January 24, 2013
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Akihiro ISHIZUKA, Shinya SASAGAWA