Patents by Inventor Akihiro Kamada

Akihiro Kamada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20090057677
    Abstract: A method for fabricating a ferroelectric device includes Step S1 of forming a polycrystalline electrode on or above a substrate in which a MOS transistor is formed, Step S2 of performing metal organic chemical vapor deposition to form an amorphous film of bismuth titanate on the polycrystalline electrode, and Step S3 of performing annealing at a temperature in a predetermined range to make the amorphous film be a polycrystalline ferroelectric film made up of a large number of bismuth titanate having a layered perovskite structure. Step S3 includes a sub-step of increasing a temperature of the amorphous film to a lower limit of the predetermined temperature range at a temperature increase rate at which crystal nuclei are not grown.
    Type: Application
    Filed: August 18, 2008
    Publication date: March 5, 2009
    Inventors: Kazunori ISOGAI, Akihiro KAMADA
  • Patent number: 6828621
    Abstract: A nonvolatile semiconductor memory device has a protective insulating film deposited on each of the side surfaces of a control gate electrode to protect the control gate electrode during the formation of a floating gate electrode, the floating gate electrode opposed to one of the side surfaces of the control gate electrode with the protective insulating film interposed therebetween so as to be capacitively coupled to the control gate electrode, a tunnel insulating film formed between the floating gate electrode and the semiconductor substrate, a drain region formed in a region of the semiconductor substrate containing a portion underlying the floating gate electrode, and a source region formed in a region of the semiconductor substrate opposite to the drain region relative to the control gate electrode.
    Type: Grant
    Filed: October 7, 2003
    Date of Patent: December 7, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Masataka Kusumi, Fumihiko Noro, Hiromasa Fujimoto, Akihiro Kamada, Shinji Odanaka, Seiki Ogura
  • Patent number: 6784040
    Abstract: A nonvolatile semiconductor memory device has a protective insulating film deposited on each of the side surfaces of a control gate electrode to protect the control gate electrode during the formation of a floating gate electrode, the floating gate electrode opposed to one of the side surfaces of the control gate electrode with the protective insulating film interposed therebetween so as to be capacitively coupled to the control gate electrode, a tunnel insulating film formed between the floating gate electrode and the semiconductor substrate, a drain region formed in a region of the semiconductor substrate containing a portion underlying the floating gate electrode, and a source region formed in a region of the semiconductor substrate opposite to the drain region relative to the control gate electrode.
    Type: Grant
    Filed: March 7, 2003
    Date of Patent: August 31, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Masataka Kusumi, Fumihiko Noro, Hiromasa Fujimoto, Akihiro Kamada, Shinji Odanaka, Seiki Ogura
  • Publication number: 20040071024
    Abstract: A nonvolatile semiconductor memory device has a protective insulating film deposited on each of the side surfaces of a control gate electrode to protect the control gate electrode during the formation of a floating gate electrode, the floating gate electrode opposed to one of the side surfaces of the control gate electrode with the protective insulating film interposed therebetween so as to be capacitively coupled to the control gate electrode, a tunnel insulating film formed between the floating gate electrode and the semiconductor substrate, a drain region formed in a region of the semiconductor substrate containing a portion underlying the floating gate electrode, and a source region formed in a region of the semiconductor substrate opposite to the drain region relative to the control gate electrode.
    Type: Application
    Filed: October 7, 2003
    Publication date: April 15, 2004
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Masataka Kusumi, Fumihiko Noro, Hiromasa Fujimoto, Akihiro Kamada, Shinji Odanaka, Seiki Ogura
  • Patent number: 6642572
    Abstract: A nonvolatile semiconductor memory device has a protective insulating film deposited on each of the side surfaces of a control gate electrode to protect the control gate electrode during the formation of a floating gate electrode, the floating gate electrode opposed to one of the side surfaces of the control gate electrode with the protective insulating film interposed therebetween so as to be capacitively coupled to the control gate electrode, a tunnel insulating film formed between the floating gate electrode and the semiconductor substrate, a drain region formed in a region of the semiconductor substrate containing a portion underlying the floating gate electrode, and a source region formed in a region of the semiconductor substrate opposite to the drain region relative to the control gate electrode.
    Type: Grant
    Filed: March 7, 2003
    Date of Patent: November 4, 2003
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Masataka Kusumi, Fumihiko Noro, Hiromasa Fujimoto, Akihiro Kamada, Shinji Odanaka, Seiki Ogura
  • Publication number: 20030173616
    Abstract: A nonvolatile semiconductor memory device has a protective insulating film deposited on each of the side surfaces of a control gate electrode to protect the control gate electrode during the formation of a floating gate electrode, the floating gate electrode opposed to one of the side surfaces of the control gate electrode with the protective insulating film interposed therebetween so as to be capacitively coupled to the control gate electrode, a tunnel insulating film formed between the floating gate electrode and the semiconductor substrate, a drain region formed in a region of the semiconductor substrate containing a portion underlying the floating gate electrode, and a source region formed in a region of the semiconductor substrate opposite to the drain region relative to the control gate electrode.
    Type: Application
    Filed: March 7, 2003
    Publication date: September 18, 2003
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Masataka Kusumi, Fumihiko Noro, Hiromasa Fujimoto, Akihiro Kamada, Shinji Odanaka, Seiki Ogura
  • Publication number: 20030141540
    Abstract: A nonvolatile semiconductor memory device has a protective insulating film deposited on each of the side surfaces of a control gate electrode to protect the control gate electrode during the formation of a floating gate electrode, the floating gate electrode opposed to one of the side surfaces of the control gate electrode with the protective insulating film interposed therebetween so as to be capacitively coupled to the control gate electrode, a tunnel insulating film formed between the floating gate electrode and the semiconductor substrate, a drain region formed in a region of the semiconductor substrate containing a portion underlying the floating gate electrode, and a source region formed in a region of the semiconductor substrate opposite to the drain region relative to the control gate electrode.
    Type: Application
    Filed: March 7, 2003
    Publication date: July 31, 2003
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Masataka Kusumi, Fumihiko Noro, Hiromasa Fujimoto, Akihiro Kamada, Shinji Odanaka, Seiki Ogura
  • Patent number: 6545312
    Abstract: A nonvolatile semiconductor memory device has a protective insulating film deposited on each of the side surfaces of a control gate electrode to protect the control gate electrode during the formation of a floating gate electrode, the floating gate electrode opposed to one of the side surfaces of the control gate electrode with the protective insulating film interposed therebetween so as to be capacitively coupled to the control gate electrode, a tunnel insulating film formed between the floating gate electrode and the semiconductor substrate, a drain region formed in a region of the semiconductor substrate containing a portion underlying the floating gate electrode, and a source region formed in a region of the semiconductor substrate opposite to the drain region relative to the control gate electrode.
    Type: Grant
    Filed: July 3, 2001
    Date of Patent: April 8, 2003
    Assignees: Matsushita Electric Industrial Co., Ltd., Halo LSI Design and Device Technologies Inc.
    Inventors: Masataka Kusumi, Fumihiko Noro, Hiromasa Fujimoto, Akihiro Kamada, Shinji Odanaka, Seiki Ogura
  • Publication number: 20020145162
    Abstract: A non-volatile semiconductor storage device includes a semiconductor substrate provided with a step portion in an upper portion thereof, and having a first region that is an upper level of the step portion and a second region that is a lower level thereof, a control gate electrode formed on the first region of the semiconductor substrate via a gate insulating film, and a floating gate electrode formed on the side face of the control gate electrode on the side of the step portion and on the step portion via an insulating film. The side face of the step portion forms an obtuse angle with respect to the upper surface of the second region, and the insulating film has a substantially uniform thickness on the step portion.
    Type: Application
    Filed: February 5, 2002
    Publication date: October 10, 2002
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.,
    Inventors: Akihiro Kamada, Hiromasa Fujimoto, Kenji Okada, Seiki Ogura
  • Patent number: 6448702
    Abstract: A cathode ray tube includes (a) an electron gun, (b) a funnel which is open at one end and in which the electron gun is located, (c) a face panel which is open at one end and connected to the funnel such that the funnel and the face panel define a closed space, (d) an internal magnetic shield which is located in the space and which is open at opposite ends such that electrons emitted from the electron gun pass therethrough and reach the face panel, (e) a mask frame which internally supports the internal magnetic shield, and (f) a shadow mask which is located in the space in facing relation with the face panel and which is supported by the mask frame. The internal magnetic shield has an edge facing to the face panel. The edge has a closed cross-section and has a projecting portion at least partially projecting from the edge towards the face panel. The projecting portion has a distal end closer to the face panel than a distal end of the shadow mask.
    Type: Grant
    Filed: September 25, 2000
    Date of Patent: September 10, 2002
    Assignee: NEC Corporation
    Inventors: Akihiro Kamada, Takashi Morohashi
  • Publication number: 20020039822
    Abstract: A nonvolatile semiconductor memory device has a protective insulating film deposited on each of the side surfaces of a control gate electrode to protect the control gate electrode during the formation of a floating gate electrode, the floating gate electrode opposed to one of the side surfaces of the control gate electrode with the protective insulating film interposed therebetween so as to be capacitively coupled to the control gate electrode, a tunnel insulating film formed between the floating gate electrode and the semiconductor substrate, a drain region formed in a region of the semiconductor substrate containing a portion underlying the floating gate electrode, and a source region formed in a region of the semiconductor substrate opposite to the drain region relative to the control gate electrode.
    Type: Application
    Filed: July 3, 2001
    Publication date: April 4, 2002
    Inventors: Masataka Kusumi, Fumihiko Noro, Hiromasa Fujimoto, Akihiro Kamada, Shinji Odanaka, Seiki Ogura
  • Publication number: 20010009349
    Abstract: A shadow mask assembly includes a mask frame and a shadow mask supported by the mask frame for extension. The mask frame is of a rectangular shape having a pair of longer side members and a pair of shorter side members. Both the edges of the shadow mask is bonded onto the longer side members while the shorter side members are bent by an external force within the elasticity thereof. After the external force is removed, the shorter side members are slightly deformed within the elasticity thereof whereas the deformation of the longer side members is substantially removed. Suitable tension can be applied to the shadow mask in a wider temperature range.
    Type: Application
    Filed: January 18, 2001
    Publication date: July 26, 2001
    Applicant: NEC Corporation
    Inventors: Yoshito Tanaka, Akihiro Kamada, Hiroshi Hasegawa, Takashi Morohashi, Nobumitsu Aibara