Abstract: Provided is an electric device made more convenient by being configured such that the temperature of a wide area in each accommodation section can be individually adjustable. In an electric device, a first refrigerant pipe is provided to a right-side member constituting a side surface of a first accommodation chamber, and a second refrigerant pipe is provided to a left-side member constituting a side surface of a second accommodation chamber. The first refrigerant pipe and the second refrigerant pipe are independent of each other. A regulating valve includes: a first regulating valve provided to the first refrigerant pipe, and a second regulating valve provided to the second refrigerant pipe.

Abstract: Provided is an electrical device. In a setting unit, a right-room temperature display unit displays a set temperature or the current temperature of a first housing room. A left-room temperature display unit displays a set temperature or the current temperature of a second housing room. A right-room temperature setting button is an operation unit for a user to switch the set temperature of the first housing room. A left-room temperature setting button is an operation unit for a user switch the set temperature of the second housing room. The set temperature difference between the first and second housing rooms is controlled to be within a prescribed value. When the set temperature of one of the first and second housing rooms is changed so that the set temperature exceeds a prescribed value, a microcomputer automatically changes the other set temperature so that the set temperature difference is within a prescribed value.

Abstract: A shape retainer and a shape retention method are provided, by which the shape of an interior space of an inner part of a baseball or softball glove can be retained precisely. A shape retainer includes a main body having a main surface depressed in a concave shape, so that the shape of the interior space of the inner part of the baseball or softball glove can be retained precisely.

Abstract: An object hardness measuring device includes a first side portion, a second side portion, a pedestal unit, a load unit, a measuring unit, and a holding unit. The load unit applies a load to the measurement object. The measuring unit is able to measure, in a state where the load acts on the measurement object, at least one of a movement distance of the second side portion with respect to the first side portion and a change amount of the load when the second side portion is moved either at a predetermined speed or to a predetermined position. The holding unit is able to hold the measurement object, and is movable between the first side portion and the second side portion by the slide rail unit.

Abstract: The baseball or softball glove includes a thumb part, an index finger pan, and a web. The web includes a first protrusion and a second protrusion. The first protrusion has a first through hole. The second protrusion has a second through hole. At least either the first through hole or the second through hole has an inclined edge that extends obliquely upward from a base of the thumb part or the index finger part on a peripheral edge forming the through hole. The first protrusion and the second protrusion are engaged with each other in a state where the first through hole and the second through hole are connected to each other in a chain shape.

Abstract: An object hardness measuring device includes a first side portion, a second side portion, a pedestal unit, a load unit, a measuring unit, and a holding unit. The load unit applies a load to the measurement object. The measuring unit is able to measure, in a state where the load acts on the measurement object, at least one of a movement distance of the second side portion with respect to the first side portion and a change amount of the load when the second side portion is moved either at a predetermined speed or to a predetermined position. The holding unit is able to hold the measurement object, and is movable between the first side portion and the second side portion by the slide rail unit.

Abstract: A high-pressure discharge lamp includes a luminous tube, an outer bulb housing the luminous tube, and a diffusing film formed on at least one of inner and outer surfaces of the outer bulb, in which the diffusing film includes first silica particles having shapes different in surface curvature from each other and hollow second silica particles.

Abstract: A metal halide lamp has an outer envelope (3, 23) of quartz glass which sounds a discharge vessel (2, 22) of quartz glass. The discharge vessel (2, 22) gas-tightly retains an ionizable fill which includes sodium. In order to avoid loss of sodium from the discharge vessel (2, 22) due to UV radiation impinging upon current supply wires (8, 9, 28, 29) extending from the discharge vessel (2, 22) within and into the outer envelope (3, 23), the quartz glass of the outer envelope is doped with materials absorbing UV radiation, preferably cerium aluminate and titanium oxide; the outer envelope is spaced from the discharge vessel by at most 5 mm, the sodium content in the ionizable fill is at most 0.7 mg.sup.3 of the discharge volume, and the space within the outer envelope is evacuated.

Abstract: A silicon oxide film and a polysilicon film are formed on a silicon substrate and are selectively etched to form a contact hole in a region where an emitter is to be formed. A polysilicon film is laid on the substrate and two polysilicon films are patterned to form an emitter electrode and a gate electrode made of the two polysilicon films which are doped with arsenic. The arsenic is diffused from the polysilicon films of the emitter electrode into the silicon substrate to form an N.sup.+ emitter layer which has a high concentration and is shallow. Consequently, the contamination of a gate insulator film can be prevented from occurring and a bipolar transistor having high performance, for example, a high current amplification factor or the like can be formed.

Abstract: A silicon oxide film and a polysilicon film are formed on a silicon substrate and are selectively etched to form a contact hole in a region where an emitter is to be formed. A polysilicon film is laid on the substrate and two polysilicon films are patterned to form an emitter electrode and a gate electrode made of the two polysilicon films which are doped with arsenic. The arsenic is diffused from the polysilicon films of the emitter electrode into the silicon substrate to form an N.sup.+ emitter layer which has a high concentration and is shallow. Consequently, the contamination of a gate insulator film can be prevented from occurring and a bipolar transistor having high performance, for example, a high current amplification factor or the like can be formed.

Abstract: A silicon oxide film as a dielectric film and a silicon nitride film or a polysilicon film as a protection film for the silicon oxide film are formed on a silicon substrate. After the two films are selectively etched to form contact holes of a bipolar transistor, a polysilicon film as a conductive film is laid on the entire substrate and selectively etched to form electrodes. In a MIS transistor, the protection film of the silicon nitride film serves as a gate insulator film and the protection film of the polysilicon film serves as a gate electrode. Accordingly, contamination to the gate insulator film at formation of contact holes of the bipolar transistor is prevented, and an excellent semiconductor with Bi-MOS structure is manufactured with low cost.

Abstract: The present invention provides a semiconductor device, in particular, a semiconductor device comprising a vertical npn transistor, a vertical pnp transistor and an IIL which are integrated on the same one-conductivity type semiconductor substrate (1) . The IIL comprises an emitter, a base and a collector which are respectively comprised of a high-density n.sup.+ -type first buried layer (5), a p.sup.+ -type second buried layer (8) having a lower impurity density than the n.sup.+ -type first buried layer (5), and at least one of n.sup.+ -type diffused layer (31). The semiconductor device thus constituted makes it possible to increase the emitter injection efficiency while the base impurity density is kept high, and also to decrease the base width, so that the collector-emitter breakdown voltage and current gain of the IIL can be more improved and also the operation speed of the IIL can be made higher.

Abstract: In a a semiconductor device having a vertical npn transistor, a vertical pnp transistor and an IIL which are integrated on the same substrate, grooves that reach an n.sup.+ -type buried layer 5 serving as an emitter of the IIL and an n.sup.+ -type buried layer 4 serving as a collector of the vertical npn transistor are formed at the same time, and an oxide film 101 is formed only on the sidewall of each groove; in the grooves, n.sup.+ -type polycrystalline silicon films 103 and 102 are formed, which are made to serve as an emitter lead-out portion of the IIL and a collector wall of the vertical npn transistor, respectively; a p-type diffused layer 17 serving as an injector of the IIL and a p-type diffused layer 18 and p.sup.

Abstract: A method of fabricating a semiconductor device includes the steps of forming a base diffusion layer in a predetermined region in a semiconductor substrate of a first conduction type, the base diffusion layer being of a second conduction type; forming first insulating films and simultaneously forming an emitter lead-out electrode and a collector lead-out electrode in regions above an emitter-contact-forming region and a collector-contact-forming region, the first insulating films extending on the emitter and collector lead-out electrodes, the emitter and collector lead-out electrodes including impurity corresponding to the first conduction type; forming second insulating films at sides of the emitter and collector lead-out electrodes; forming a base contact; forming a base lead-out electrode including impurity corresponding to the second conduction type; diffusing the impurity from the emitter lead-out electrode, the collector lead-out electrode, and the base lead-out electrode to form an emitter diffusion lay

Abstract: A method of fabricating a semiconductor device includes the steps of forming a base diffusion layer in a predetermined region in a semiconductor substrate of a first conduction type, the base diffusion layer being of a second conduction type; forming first insulating films and simultaneously forming an emitter lead-out electrode and a collector lead-out electrode in regions above an emitter-contact-forming region and a collector-contact-forming region, the first insulating extending films on the emitter and collector lead-out electrodes, the emitter and collector lead-out electrodes including impurity corresponding to the first conduction type; forming second insulating films at sides of the emitter and collector lead-out electrodes; forming a base contact; forming a base lead-out electrode including impurity corresponding to the second conduction type; diffusing the impurity from the emitter lead-out electrode, the collector lead-out electrode, and the base lead-out electrode to form an emitter diffusion lay

Abstract: The present invention provides a semiconductor device, in particular, a semiconductor device comprising a vertical npn transistor, a vertical pnp transistor and an IIL which are integrated on the same one-conductivity type semiconductor substrate (1). The IIL comprises an emitter, a base and a collector which are respectively comprised of a high-density n.sup.+ -type first buried layer (5), a p.sup.+ -type second buried layer (8) having a lower impurity density than the n.sup.+ -type first buried layer (5), and at least one of n.sup.+ -type diffused layer (31).The semiconductor device thus constituted makes it possible to increase the emitter injection efficiency while the base impurity density is kept high, and also to decrease the base width, so that the collector-emitter breakdown voltage and current gain of the IIL can be more improved and also the operation speed of the IIL can be made higher.

Abstract: In making a vertical bipolar transistors, after forming by diffusion process a region to become inactive base region an oxide film is selectively formed on the region, thereafter an ion implantation is carried out to produce regions which become the active base region and emitter region by using the oxide film; thereby such a configuration is formed so that defect part (108) induced at the time of the ion implantation is confined in the emitter region, thereby minimizing the leakage current at the PN junction, and hence assuring production of high performance and high reliability semiconductor devices; further, a high integration is attained by adopting self-alignment in forming emitter contact.