Patents by Inventor Akihiro Maesaka
Akihiro Maesaka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230418016Abstract: A fixing structure according to one embodiment of the present disclosure is a fixing structure including a first object and a second object that are fixed to each other with an adhesive. The first object has a first adhesive face in contact with the adhesive. The second object has a second adhesive face that faces the first adhesive face, and an extended face that is provided on at least a part of an entire periphery surrounding the adhesive about an axis perpendicular to the second adhesive face and extends in a direction parallel to the axis perpendicular to the second adhesive face. The adhesive is in contact with the second adhesive face of the second object, whereas not in contact with the extended face.Type: ApplicationFiled: October 13, 2021Publication date: December 28, 2023Inventors: AKIHIRO MAESAKA, TAKUMI OKITA
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Publication number: 20210271048Abstract: Provided is a securing structure for an optical component enabling stress generated when adhesive for securing an optical component is cured and shrunk to be reduced and enabling distortion of the optical component to be suppressed. Provided is a securing structure for an optical component including an optical component, and an adhesive portion that is in contact with a holding portion for the optical component. The adhesive portion includes a first adhesive cured material layer and a second adhesive cured material layer, the first adhesive cured material layer is located between the optical component and the second adhesive cured material layer, and a storage elastic modulus of the first adhesive cured material layer is lower than a storage elastic modulus of the second adhesive cured material layer.Type: ApplicationFiled: June 7, 2019Publication date: September 2, 2021Inventors: AKIHIRO MAESAKA, TAKUMI OKITA, YUKIKO MIZUGUCHI
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Patent number: 9577187Abstract: The present invention provides a memory element and a memory device realizing reduced variations in resistance values in an initial state or erase state of a plurality of memory elements and capable of retaining the resistance value in a write/erase state for writing/erasing operations of a plurality of times. The memory element includes a first electrode, a memory layer, and a second electrode in order. The memory layer has: an ion source layer containing at least one of chalcogen elements of tellurium (Te), sulfur (S), and selenium (Se) and at least one metal element selected from copper (Cu), silver (Ag), zinc (Zn), and zirconium (Zr); and two or more high-resistance layers having a resistance value higher than that of the ion source layer and having different compositions.Type: GrantFiled: July 24, 2015Date of Patent: February 21, 2017Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Akihiro Maesaka, Kazuhiro Ohba, Tetsuya Mizuguchi, Koji Miyata, Motonari Honda, Katsuhisa Aratani
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Publication number: 20150333256Abstract: The present invention provides a memory element and a memory device realizing reduced variations in resistance values in an initial state or erase state of a plurality of memory elements and capable of retaining the resistance value in a write/erase state for writing/erasing operations of a plurality of times. The memory element includes a first electrode, a memory layer, and a second electrode in order. The memory layer has: an ion source layer containing at least one of chalcogen elements of tellurium (Te), sulfur (S), and selenium (Se) and at least one metal element selected from copper (Cu), silver (Ag), zinc (Zn), and zirconium (Zr); and two or more high-resistance layers having a resistance value higher than that of the ion source layer and having different compositions.Type: ApplicationFiled: July 24, 2015Publication date: November 19, 2015Inventors: Akihiro Maesaka, Kazuhiro Ohba, Tetsuya Mizuguchi, Koji Miyata, Motonari Honda, Katsuhisa Aratani
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Patent number: 9136470Abstract: The present invention provides a memory element and a memory device realizing reduced variations in resistance values in an initial state or erase state of a plurality of memory elements and capable of retaining the resistance value in a write/erase state for writing/erasing operations of a plurality of times. The memory element includes a first electrode, a memory layer, and a second electrode in order. The memory layer has: an ion source layer containing at least one of chalcogen elements of tellurium (Te), sulfur (S), and selenium (Se) and at least one metal element selected from copper (Cu), silver (Ag), zinc (Zn), and zirconium (Zr); and two or more high-resistance layers having a resistance value higher than that of the ion source layer and having different compositions.Type: GrantFiled: December 1, 2010Date of Patent: September 15, 2015Assignee: SONY CORPORATIONInventors: Akihiro Maesaka, Kazuhiro Ohba, Tetsuya Mizuguchi, Koji Miyata, Motonari Honda, Katsuhisa Aratani
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Patent number: 8981325Abstract: A memory device 10 has an arrangement in which a memory thin film 4 is sandwiched between first and second electrodes 2 and 6, the memory thin film 6 contains at least rare earth elements, the memory thin film 4 or a layer 3 in contact with the memory thin film 4 contains any one of elements selected from Cu, Ag, Zn and the memory thin film 4 or the layer 3 in contact with the memory thin film 4 contains any one of elements selected from Te, S, Se. The memory device can record and read information with ease stably, and this memory device can be manufactured easily by a relatively simple manufacturing method.Type: GrantFiled: February 10, 2010Date of Patent: March 17, 2015Assignee: Sony CorporationInventors: Katsuhisa Aratani, Akihiro Maesaka, Akira Kouchiyama, Tomohito Tsushima
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Patent number: 8884397Abstract: A memory device 10 having an arrangement in which a memory thin film is sandwiched between first and second electrodes, the memory thin film contains at least rare earth elements, the memory thin film 4 or a layer in contact with the memory thin film contains any one of elements selected from Cu, Ag, Zn and the memory thin film or the layer in contact with the memory thin film contains any one of elements selected from Te, S, Se.Type: GrantFiled: December 6, 2010Date of Patent: November 11, 2014Assignee: Sony CorporationInventors: Katsuhisa Aratani, Akihiro Maesaka, Akira Kouchiyama, Tomohito Tsushima
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Patent number: 8871672Abstract: In one example embodiment, a core-shell type platinum-containing catalyst is allowed to reduce the amount of used platinum and has high catalytic activity and stability. In one example embodiment, the core-shell type platinum-containing catalyst includes a core particle (with an average particle diameter R1) made of a non-platinum element and a platinum shell layer (with an average thickness ts) satisfying 1.4 nm?R1?3.5 nm and 0.25 nm?ts?0.9 nm. The core particle includes an element satisfying Eout?3.0 eV, where average binding energy relative to the Fermi level of 5d orbital electrons of platinum present on an outermost surface of the shell layer is Eout. In a fuel cell including a platinum-containing catalyst which contains a Ru particle as a core particle, the output density at a current density of 300 mA/cm2 is 70 mW/cm2 or over, and an output retention ratio is approximately 90% or over.Type: GrantFiled: October 29, 2009Date of Patent: October 28, 2014Assignee: Sony CorporationInventors: Shuji Goto, Shizuka Hosoi, Yuli Li, Yoshihiro Kudo, Akihiro Maesaka
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Publication number: 20110275009Abstract: A core-shell type platinum-containing catalyst being allowed to reduce the amount of used platinum and having high catalytic activity and stability and a method of producing the same, an electrode and an electrochemical device are provided. The platinum-containing catalyst includes: metal particles each including a core particle including a metal atom except for platinum or an alloy of a metal atom except for platinum and a shell layer, including platinum on a surface of the core particle, the metal particles being supported by a conductive carrier and satisfying 0.25 nm?ts?0.9 nm and 1.4 nm?R1?3.5 nm, where an average thickness of the shell layer is ts and an average particle diameter of the core particle is R1.Type: ApplicationFiled: July 20, 2011Publication date: November 10, 2011Applicant: SONY CORPORATIONInventors: Shuji Goto, Shizuka Hosoi, Yuli Li, Yoshihiro Kudo, Akihiro Maesaka
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Publication number: 20110200915Abstract: In one example embodiment, a core-shell type platinum-containing catalyst is allowed to reduce the amount of used platinum and has high catalytic activity and stability. In one example embodiment, the core-shell type platinum-containing catalyst includes a core particle (with an average particle diameter R1) made of a non-platinum element and a platinum shell layer (with an average thickness ts) satisfying 1.4 nm?R1?3.5 nm and 0.25 nm?ts?0.9 nm. The core particle includes an element satisfying Eout?3.0 eV, where average binding energy relative to the Fermi level of 5d orbital electrons of platinum present on an outermost surface of the shell layer is Eout. In a fuel cell including a platinum-containing catalyst which contains a Ru particle as a core particle, the output density at a current density of 300 mA/cm2 is 70 mW/cm2 or over, and an output retention ratio is approximately 90% or over.Type: ApplicationFiled: October 29, 2009Publication date: August 18, 2011Applicant: SONY CORPORATIONInventors: Shuji Goto, Shizuka Hosoi, Yuli Li, Yoshihiro Kudo, Akihiro Maesaka
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Publication number: 20110140065Abstract: The present invention provides a memory element and a memory device realizing reduced variations in resistance values in an initial state or erase state of a plurality of memory elements and capable of retaining the resistance value in a write/erase state for writing/erasing operations of a plurality of times. The memory element includes a first electrode, a memory layer, and a second electrode in order. The memory layer has: an ion source layer containing at least one of chalcogen elements of tellurium (Te), sulfur (S), and selenium (Se) and at least one metal element selected from copper (Cu), silver (Ag), zinc (Zn), and zirconium (Zr); and two or more high-resistance layers having a resistance value higher than that of the ion source layer and having different compositions.Type: ApplicationFiled: December 1, 2010Publication date: June 16, 2011Applicant: SONY CORPORATIONInventors: Akihiro Maesaka, Kazuhiro Ohba, Tetsuya Mizuguchi, Koji Miyata, Motonari Honda, Katsuhisa Aratani
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Publication number: 20110073825Abstract: A memory device 10 having an arrangement in which a memory thin film is sandwiched between first and second electrodes, the memory thin film contains at least rare earth elements, the memory thin film 4 or a layer in contact with the memory thin film contains any one of elements selected from Cu, Ag, Zn and the memory thin film or the layer in contact with the memory thin film contains any one of elements selected from Te, S, Se.Type: ApplicationFiled: December 6, 2010Publication date: March 31, 2011Applicant: SONY CORPORATIONInventors: Katsuhisa Aratani, Akihiro Maesaka, Akira Kouchiyama, Tomohito Tsushima
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Publication number: 20100135060Abstract: A memory device 10 has an arrangement in which a memory thin film 4 is sandwiched between first and second electrodes 2 and 6, the memory thin film 6 contains at least rare earth elements, the memory thin film 4 or a layer 3 in contact with the memory thin film 4 contains any one of elements selected from Cu, Ag, Zn and the memory thin film 4 or the layer 3 in contact with the memory thin film 4 contains any one of elements selected from Te, S, Se. The memory device can record and read information with ease stably, and this memory device can be manufactured easily by a relatively simple manufacturing method.Type: ApplicationFiled: February 10, 2010Publication date: June 3, 2010Applicant: SONY CORPORATIONInventors: Katsuhisa Aratani, Akihiro Maesaka, Akira Kouchiyama, Tomohito Tsushima
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Patent number: 7719082Abstract: A memory device 10 has an arrangement in which a memory thin film 4 is sandwiched between first and second electrodes 2 and 6, the memory thin film 6 contains at least rare earth elements, the memory thin film 4 or a layer 3 in contact with the memory thin film 4 contains any one of elements selected from Cu, Ag, Zn and the memory thin film 4 or the layer 3 in contact with the memory thin film 4 contains any one of elements selected from Te, S, Se. The memory device can record and read information with ease stably, and this memory device can be manufactured easily by a relatively simple manufacturing method.Type: GrantFiled: November 17, 2004Date of Patent: May 18, 2010Assignee: Sony CorporationInventors: Katsuhisa Aratani, Akihiro Maesaka, Akira Kouchiyama, Tomohito Tsushima
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Patent number: 7675053Abstract: A memory element in which data recording and data readout can be performed stably without difficulties and which can be manufactured with a comparatively simplified method is provided. The memory element 10 includes a memory layer 4 and an ion source layer 3 positioned between the first electrode 2 and the second electrode 6, in which the ion source layer 3 contains any of elements selected from Cu, Ag, Zn and any of elements selected from Te, S, Se, and the ion source layer further contains boron (or rare-earth elements and silicon).Type: GrantFiled: January 9, 2006Date of Patent: March 9, 2010Assignee: Sony CorporationInventors: Tetsuya Mizuguchi, Katsuhisa Aratani, Akihiro Maesaka, Akira Kouchiyama
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Patent number: 7193287Abstract: This invention proposes a stable magnetic memory device that is equipped with a storage cell having a MTJ, wherein variation in the coercive force (Hc) of a ferromagnetic free layer is suppressed, and a switching characteristic of a bit of a MRAM is improved, and there is no write error. Namely in a magnetic memory device equipped with a first wiring, a second wiring (bit line) intersecting with the first wiring, and a storage cell for writing/reading information of a magnetic spin at an intersecting area of the first wiring and the second wiring, a partial sidewall portion electrically connecting to the storage cell of the second wiring (bit line) has a forward tapered form having a contact angle relative to a top surface of the storage cell being 45 degrees or more.Type: GrantFiled: January 23, 2004Date of Patent: March 20, 2007Assignee: Sony CorporationInventor: Akihiro Maesaka
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Publication number: 20060189084Abstract: A memory element in which data recording and data readout can be performed stably without difficulties and which can be manufactured with a comparatively simplified method is provided. The memory element 10 includes a memory layer 4 and an ion source layer 3 positioned between the first electrode 2 and the second electrode 6, in which the ion source layer 3 contains any of elements selected from Cu, Ag, Zn and any of elements selected from Te, S, Se, and the ion source layer further contains boron (or rare-earth elements and silicon).Type: ApplicationFiled: January 9, 2006Publication date: August 24, 2006Applicant: Sony CorporationInventors: Tetsuya Mizuguchi, Katsuhisa Aratani, Akihiro Maesaka, Akira Kouchiyama
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Publication number: 20050226036Abstract: A memory device 10 has an arrangement in which a memory thin film 4 is sandwiched between first and second electrodes 2 and 6, the memory thin film 6 contains at least rare earth elements, the memory thin film 4 or a layer 3 in contact with the memory thin film 4 contains any one of elements selected from Cu, Ag, Zn and the memory thin film 4 or the layer 3 in contact with the memory thin film 4 contains any one of elements selected from Te, S, Se. The memory device can record and read information with ease stably, and this memory device can be manufactured easily by a relatively simple manufacturing method.Type: ApplicationFiled: November 17, 2004Publication date: October 13, 2005Inventors: Katsuhisa Aratani, Akihiro Maesaka, Akira Kouchiyama, Tomohito Tsushima
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Publication number: 20040233757Abstract: This invention proposes a stable magnetic memory device that is equipped with a storage cell having a MTJ, wherein variation in the coercive force (Hc) of a ferromagnetic free layer is suppressed, and a switching characteristic of a bit of a MRAM is improved, and there is no write error. Namely in a magnetic memory device equipped with a first wiring, a second wiring (bit line) intersecting with the first wiring, and a storage cell for writing/reading information of a magnetic spin at an intersecting area of the first wiring and the second wiring, a partial sidewall portion electrically connecting to the storage cell of the second wiring (bit line) has a forward tapered form having a contact angle relative to a top surface of the storage cell being 45 degrees or more.Type: ApplicationFiled: January 23, 2004Publication date: November 25, 2004Inventor: Akihiro Maesaka
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Patent number: 6596418Abstract: To provide a magnetic recording medium which greatly decreases a transition noise in a layered magnetic recording layer, excels in an S/N ratio, and is suited for short wavelength recording, the magnetic recording medium includes a vertical magnetic recording film comprising an artificial lattice film formed by alternately layering a Pt or Pd layer and a Co layer and containing B and O elements.Type: GrantFiled: June 26, 2001Date of Patent: July 22, 2003Assignee: Sony CorporationInventors: Akihiro Maesaka, Hiroyuki Ohmori