Patents by Inventor Akihiro Matsuda
Akihiro Matsuda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6294438Abstract: A semiconductor device forming a capacitor through an interlayer insulating layer on a semiconductor substrate on which an integrated circuit is formed. This semiconductor device has an interlayer insulating layer with moisture content of 0.5 g/cm3 or less, which covers the capacitor in one aspect, and has a passivation layer with hydrogen content of 1021 atoms/cm3 or less, which covers the interconnections of the capacitor in other aspect. By thus constituting, deterioration of the capacitor dielectric can be prevented which brings about the electrical reliability of the ferroelectric layer or high dielectric layer.Type: GrantFiled: June 8, 2000Date of Patent: September 25, 2001Assignee: Matsushita Electronics CorporationInventors: Koji Arita, Eiji Fujii, Yasuhiro Shimada, Yasuhiro Uemoto, Toru Nasu, Akihiro Matsuda, Yoshihisa Nagano, Atsuo Inoue, Taketoshi Matsuura, Tatsuo Otsuki
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Publication number: 20010020709Abstract: The semiconductor device of the invention includes a capacitor device, which is formed on a substrate and which includes a capacitive lower electrode, a capacitive insulating film made of an insulating metal oxide film and a capacitive upper electrode. An interlevel insulating film having an opening reaching the capacitive upper electrode is formed over the capacitor device. A metal interconnection including a titanium film is formed over the interlevel insulating film so as to be electrically connected to the capacitive upper electrode through the opening. An anti-diffusion film having conductivity is formed between the capacitive upper electrode and the metal interconnection for preventing titanium atoms composing the titanium film of the metal interconnection from passing through the capacitive upper electrode and diffusing into the capacitive insulating film.Type: ApplicationFiled: March 5, 2001Publication date: September 13, 2001Applicant: Matsushita Electronics CorporationInventors: Keisaku Nakao, Akihiro Matsuda, Yasufumi Izutsu, Toyoji Ito, Takumi Mikawa, Toru Nasu, Yoshihisa Nagano, Keisuke Tanaka, Toshie Kutsunai
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Patent number: 6239462Abstract: The semiconductor device of the invention includes a capacitor device, which is formed on a substrate and which includes a capacitive lower electrode, a capacitive insulating film made of an insulating metal oxide film and a capacitive upper electrode. An interlevel insulating film having an opening reaching the capacitive upper electrode is formed over the capacitor device. A metal interconnection including a titanium film is formed over the interlevel insulating film so as to be electrically connected to the capacitive upper electrode through the opening. An anti-diffusion film having conductivity is formed between the capacitive upper electrode and the metal interconnection for preventing titanium atoms composing the titanium film of the metal interconnection from passing through the capacitive upper electrode and diffusing into the capacitive insulating film.Type: GrantFiled: July 23, 1998Date of Patent: May 29, 2001Assignee: Matsushita Electronics CorporationInventors: Keisaku Nakao, Akihiro Matsuda, Yasufumi Izutsu, Toyoji Ito, Takumi Mikawa, Toru Nasu, Yoshihisa Nagano, Keisuke Tanaka, Toshie Kutsunai
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Patent number: 6174213Abstract: Metal organic precursor compounds are dissolved in an organic solvent to form a nonaqueous liquid precursor. The liquid precursor is applied to the inner envelope surface of a fluorescent lamp and heated to form a metal oxide thin film layer. The metal oxide thin film layer may be a conductor, a protective layer or provide other functions. The films have a thickness of from 20 nm to 500 nm. A conductive layer comprising tin-antimony oxide with niobium dopant may be fabricated to have a differential resistivity profile by selecting a combination of precursor composition and annealing temperatures.Type: GrantFiled: September 1, 1999Date of Patent: January 16, 2001Assignees: Symetrix Corporation, Matsushita Electronics CorporationInventors: Carlos A. Paz de Araujo, Jolanta Celinska, Joseph D. Cuchiaro, Jeffrey W. Bacon, Larry D. McMillan, Akihiro Matsuda, Gota Kano, Yoshio Yamaguchi, Tatsuo Morita, Hideo Nagai
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Patent number: 6169304Abstract: A semiconductor device forming a capacitor through an interlayer insulating layer on a semiconductor substrate on which an integrated circuit is formed. This semiconductor device has an interlayer insulating layer with moisture content of 0.5 g/cm3 or less, which covers the capacitor in one aspect, and has a passivation layer with hydrogen content of 1021 atoms/cm3 or less, which covers the interconnections of the capacitor in other aspect. By thus constituting, deterioration of the capacitor dielectric can be prevented which brings about the electrical reliability of the ferroelectric layer or high dielectric layer.Type: GrantFiled: May 4, 1998Date of Patent: January 2, 2001Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Koji Arita, Eiji Fujii, Yasuhiro Shimada, Yasuhiro Uemoto, Toru Nasu, Akihiro Matsuda, Yoshihisa Nagano, Atsuo Inoue, Taketoshi Matsuura, Tatsuo Otsuki
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Patent number: 6143597Abstract: A method of manufacturing a capacitor comprises a step of forming a first dielectric layer composed of a ferroelectric material or a dielectric material possessing high permittivity on a first electrode, a step of sintering the first dielectric layer, a step of forming a second dielectric layer on the first dielectric layer, and a step of forming a second electrode on the second dielectric layer. By forming the second dielectric layer having small crystal grain size on the first dielectric layer having large crystal grain size, the surface of the capacitor insulating layer becomes flat.Type: GrantFiled: July 12, 1996Date of Patent: November 7, 2000Assignee: Matsushita Electronics CorporationInventors: Akihiro Matsuda, Yoshihisa Nagano, Toru Nasu, Koji Arita, Yasuhiro Uemoto
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Patent number: 6126752Abstract: A semiconductor device comprising an integrated circuit and a capacitor. In this capacitor, a bottom electrode, a dielectric film and a top electrode are formed, independently of the integrated circuit, on the interlayer insulating film, and the top electrode and bottom electrode are connected with metal interconnections through contact holes opened in the protective film for protecting the surface of the capacitor. In this constitution, either the top electrode or the bottom electrode is connected the bias line of the integrated circuit, and the other is connected to the ground line, so that extraneous emission may be reduced without having to connect the capacitor outside.Type: GrantFiled: October 9, 1997Date of Patent: October 3, 2000Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Eiji Fujii, Yasuhiro Shimada, Yasuhiro Uemoto, Shinitirou Hayashi, Tooru Nasu, Koichi Arita, Atsuo Inoue, Akihiro Matsuda, Masaki Kibe, Tatsuo Ootsuki
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Patent number: 6107657Abstract: A semiconductor device forming a capacitor through an interlayer insulating layer on a semiconductor substrate on which an integrated circuit is formed. This semiconductor device has an interlayer insulating layer with moisture content of 0.5 g/cm.sup.3 or less, which covers the capacitor in one aspect, and has a passivation layer with hydrogen content of 10.sup.21 atoms/cm.sup.3 or less, which covers the interconnections of the capacitor in other aspect. By thus constituting, deterioration of the capacitor dielectric can be prevented which brings about the electrical reliability of the ferroelectric layer or high dielectric layer.Type: GrantFiled: May 4, 1998Date of Patent: August 22, 2000Assignee: Matsushita Electronics CorporationInventors: Koji Arita, Eiji Fujii, Yasuhiro Shimada, Yasuhiro Uemoto, Toru Nasu, Akihiro Matsuda, Yoshihisa Nagano, Atsuo Inoue, Taketoshi Matsuura, Tatsuo Otsuki
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Patent number: 6080617Abstract: A semiconductor device comprising an integrated circuit and a capacitor. In this capacitor, a bottom electrode, a dielectric film and a top electrode are formed, independently of the integrated circuit, on the interlayer insulating film, and the top electrode and bottom electrode are connected with metal interconnections through contact holes opened in the protective film for protecting the surface of the capacitor. In this constitution, either the top electrode or the bottom electrode is connected the bias line of the integrated circuit, and the other is connected to the ground line, so that extraneous emission may be reduced without having to connect the capacitor outside.Type: GrantFiled: October 15, 1997Date of Patent: June 27, 2000Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Eiji Fujii, Yasuhiro Shimada, Yasuhiro Uemoto, Shinitirou Hayashi, Tooru Nasu, Koichi Arita, Atsuo Inoue, Akihiro Matsuda, Masaki Kibe, Tatsuo Ootsuki
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Patent number: 6046467Abstract: A capacitor 25 is formed on an insulating layer 21a formed on a semiconductor substrate 21. The end portion of a capacitor insulating layer 23 is positioned between the end portion of a bottom electrode 22 and the end portion of a top electrode 24. A passivation layer 26 for covering the capacitor 25 is formed. Interconnections 28 are connected to the bottom electrode 22 through a first hole 27a and to the top electrode 24 through a second hole 27b. In this way, since the end portion of the capacitor insulating layer 23 is out of the end portion of the top electrode 24, the end portion of the capacitor insulating layer 23 injured by etching does not affect the capacitance.Type: GrantFiled: June 20, 1996Date of Patent: April 4, 2000Assignee: Matsushita Electronics CorporationInventors: Koji Arita, Akihiro Matsuda, Yoshihisa Nagano, Toru Nasu, Eiji Fujii
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Patent number: 6046490Abstract: A semiconductor device is provided with a multilayered interconnection and a capacitor dielectric element, in which the transistor in the device has a non-degraded characteristics and the degradation of the capacitor dielectric element is suppressed. The semiconductor device has wiring layers connecting to one another through contact holes in insulating layers. One of the insulating layers is formed so as to cover at least a part of the area above the transistor and so as not to cover the area above the capacitor dielectric element. Hydrogen generated by heat-treating the insulating layer is supplied to the transistor to recover the damage in it, while hydrogen is suppressed from arriving at the capacitor element so that the capacitor dielectric element does not degrade.Type: GrantFiled: August 10, 1998Date of Patent: April 4, 2000Assignee: Matsushita Electronics CorporationInventors: Koji Arita, Eiji Fujii, Yasuhiro Uemoto, Yoshihisa Nagano, Akihiro Matsuda
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Patent number: 6015987Abstract: A semiconductor device forming a capacitor through an interlayer insulating layer on a semiconductor substrate on which an integrated circuit is formed. This semiconductor device has an interlayer insulating layer with moisture content of 0.5 g/cm.sup.3 or less, which covers the capacitor in one aspect, and has a passivation layer with hydrogen content of 10.sup.21 atoms/cm.sup.3 or less, which covers the interconnections of the capacitor in other aspect. By thus constituting, deterioration of the capacitor dielectric can be prevented which brings about the electrical reliability of the ferroelectric layer or high dielectric layer.Type: GrantFiled: May 4, 1998Date of Patent: January 18, 2000Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Koji Arita, Eiji Fujii, Yasuhiro Shimada, Yasuhiro Uemoto, Toru Nasu, Akihiro Matsuda, Yoshihisa Nagano, Atsuo Inoue, Taketoshi Matsuura, Tatsuo Otsuki
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Patent number: 5943568Abstract: A method of making a semiconductor device include forming: (a) a semiconductor substrate on whose surface an integrated circuit is formed, (b) a first insulating layer on the semiconductor device and having first contact holes which lead to the integrated circuit, (c) a capacitance element on the first insulating layer, (d) a second insulating layer on the first insulating layer to cover the capacitance element, and having second contact holes which lead to an upper and a lower electrodes of the capacitance element respectively, and (e) interconnections which are connected to the integrated circuit and the capacitance element respectively through the first and second contact holes. The hydrogen density of this semiconductor device is 10.sup.11 atoms/cm.sup.2 or less.Type: GrantFiled: March 5, 1997Date of Patent: August 24, 1999Assignee: Matsushita Electronics CorporationInventors: Eiji Fujii, Atsuo Inoue, Koji Arita, Toru Nasu, Akihiro Matsuda
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Patent number: 5837591Abstract: A semiconductor device comprises silicon substrate 1 on which an integrated circuit is formed, first insulating layer 6 formed on silicon substrate 1, a capacitor comprising lower electrode 7 formed on first insulating layer 6, dielectric film 8 having a high dielectric constant and upper electrode 9, a second insulating film 11 having contact holes 13 which lead to lower electrode 7 and upper electrode 9 independently, diffusion barrier layer 17 which touches lower electrode 7 and upper electrode 9 at bottom of contact holes 13, and interconnection layer 15 formed on diffusion barrier layer 17. In diffusion barrier layer 17 at the bottom of contact hole 13, a lamellar region made of granular crystal is formed.Type: GrantFiled: February 19, 1997Date of Patent: November 17, 1998Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Yasuhiro Shimada, Atsuo Inoue, Koji Arita, Toru Nasu, Yoshihisa Nagano, Akihiro Matsuda
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Patent number: 5795794Abstract: The present invention relates to method of manufacturing semiconductor devices having built-in capacitor comprising a dielectric substance of high dielectric constant or a ferroelectric substance as the capacitance insulation film, and aims to solve a problem that the prior art capacitance insulation film contained in semiconductor devices has a rough surface which results in a poor insulating voltage and a large spread in electrical characteristics, as well as broken connection wire; in which method a capacitance insulation film is produced by first forming a first dielectric film, and forming a second dielectric film on the first dielectric film for a thickness greater than the difference in level between top and bottom of the surface of first dielectric film, and forming a thin film whose etching speed is identical with that of the second dielectric film on the second dielectric film making the surface of thin film flat, and then etching the whole of the thin film and part of the second dielectric film offType: GrantFiled: July 11, 1996Date of Patent: August 18, 1998Assignee: Matsushita Electronics CorporationInventors: Yoshihisa Nagano, Eiji Fujii, Toru Nasu, Akihiro Matsuda
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Patent number: 5780351Abstract: A semi conductor device forming a capacitor through an interlayer insulating layer on a semiconductor substrate on which an integrated circuit is formed. This semiconductor device has an interlayer insulating layer with moisture content of 0.5 g/cm.sup.3 or less, which covers the capacitor in one aspect, and has a passivation layer with hydrogen content of 10.sup.21 atoms/cm.sup.3 or less, which covers the interconnections of the capacitor in other aspect. By thus constituting, deterioration of the capacitor dielectric can be prevented which brings about the electrical reliability of the ferroelectric layer or high dielectric layer.Type: GrantFiled: April 28, 1997Date of Patent: July 14, 1998Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Koji Arita, Eiji Fujii, Yasuhiro Shimada, Yasuhiro Uemoto, Toru Nasu, Akihiro Matsuda, Yoshihisa Nagano, Atsuo Inoue, Taketoshi Matsuura, Tatsuo Otsuki
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Patent number: 5717233Abstract: A semiconductor device comprising an integrated circuit and a capacitor. In this capacitor, a bottom electrode, a dielectric film and a top electrode are formed, independently of the integrated circuit, on the interlayer insulating film, and the top electrode and bottom electrode are connected with metal interconnections through contact holes opened in the protective film for protecting the surface of the capacitor. In this constitution, either the top electrode or the bottom electrode is connected the bias line of the integrated circuit, and the other is connected to the ground line, so that extraneous emission may be reduced without having to connect the capacitor outside.Type: GrantFiled: January 6, 1997Date of Patent: February 10, 1998Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Eiji Fujii, Yasuhiro Shimada, Yasuhiro Uemoto, Shinitirou Hayashi, Tooru Nasu, Koichi Arita, Atsuo Inoue, Akihiro Matsuda, Masaki Kibe, Tatsuo Ootsuki
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Patent number: 5661319Abstract: This is a semiconductor device having an integrated circuit and a capacitor formed on a semiconductor substrate. The capacitor comprises a bottom electrode serving also as a part of a diffusion layer of the integrated circuit, a dielectric film being formed on the bottom electrode, and a top electrode of a conductive film being formed on the dielectric film. In particular, it is preferred to form the dielectric film in two layers of dielectric film, and compose the dielectric film contacting with the bottom electrode of a dielectric material in a composition possessing an excess of a metal element than the stoichiometric composition.Type: GrantFiled: July 22, 1996Date of Patent: August 26, 1997Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Eiji Fujii, Yasuhiro Shimada, Yasuhiro Uemoto, Tooru Nasu, Akihiro Matsuda, Tatsuo Ootsuki
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Patent number: 5644158Abstract: A semiconductor device comprising: (a) a semiconductor substrate on whose surface an integrated circuit is formed, (b) a first insulating layer formed on the semiconductor device and having first contact holes which lead to the integrated circuit, (c) a capacitance element formed on the first insulating layer, (d) a second insulating layer formed on the first insulating layer to cover the capacitance element, and having second contact holes which lead to an upper and a lower electrodes of the capacitance element respectively, and (e) interconnections which are connected to the integrated circuit and the capacitance element respectively through the first and second contact holes. The hydrogen density of this semiconductor device is 10.sup.11 atoms/cm.sup.2 or less.Type: GrantFiled: June 20, 1995Date of Patent: July 1, 1997Assignee: Matsushita Electronics CorporationInventors: Eiji Fujii, Atsuo Inoue, Koji Arita, Toru Nasu, Akihiro Matsuda
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Patent number: 5627391Abstract: A semiconductor device comprises silicon substrate 1 on which an integrated circuit is formed, first insulating layer 6 formed on silicon substrate 1, a capacitor comprising lower electrode 7 formed on first insulating layer 6, dielectric film 8 having a high dielectric constant and upper electrode 9, a second insulating film 11 having contact holes 13 which lead to lower electrode 7 and upper electrode 9 independently, diffusion barrier layer 17 which touches lower electrode 7 and upper electrode 9 at the bottom of contact holes 13, and interconnection layer 15 formed on diffusion barrier layer 17. In diffusion barrier layer 17 at the bottom of contact hole 13, a lamellar region made of granular crystal is formed.Type: GrantFiled: June 20, 1995Date of Patent: May 6, 1997Assignee: Matsushita Electronics CorporationInventors: Yasuhiro Shimada, Atsuo Inoue, Koji Arita, Toru Nasu, Yoshihisa Nagano, Akihiro Matsuda