Abstract: A printer includes a processor configured to be communicatively coupled to an external device and a POS terminal on which a web browser operates, and enabling control of the external device by a control object with respect to the POS terminal based on relationship information, in which the processor enables the control of the external device by the control object with respect to a first POS terminal based on first relationship information, deletes the first relationship information while the control object is not deleted when the control of the external device by the first POS terminal ends, generates second relationship information indicating a relationship between a second POS terminal and the control object when a request for the external device from the second POS terminal is received after deleting the first relationship information, and enables the control of the external device from the second POS terminal by the control object.

Abstract: A printer includes a processor configured to be communicatively coupled to an external device and a POS terminal on which a web browser operates, and enabling control of the external device by a control object with respect to the POS terminal based on relationship information, in which the processor enables the control of the external device by the control object with respect to a first POS terminal based on first relationship information, deletes the first relationship information while the control object is not deleted when the control of the external device by the first POS terminal ends, generates second relationship information indicating a relationship between a second POS terminal and the control object when a request for the external device from the second POS terminal is received after deleting the first relationship information, and enables the control of the external device from the second POS terminal by the control object.

Abstract: An improved semiconductor memory device capable of easily detecting the location of a defective bit line and a defective memory cell as a leakage current path for a short time is provided. A region flowing a leakage current no smaller than a predetermined value is determined by detecting one of a first large region and a remaining second large region, either of said first and second large regions being selected by simultaneously selecting a predetermined number of said column selection lines. Then, a region flowing a leakage current no smaller than a predetermined value is determined by detecting one of a first small region and a remaining second small region, said first and second small regions constituting said one of the first and second large regions, either of said first and second small regions being selected by simultaneously selecting a predetermined number of said column selection lines. For this purpose, an address signal output control circuit is provided within the semiconductor memory device.

Abstract: A semiconductor memory device includes bit lines and word lines arranged lengthwise and breadthwise, memory cells 1 capable of reading out and writing in, MOS transistors Q1 and Q2 for pre-charge, MOS transistors Q3 for short-circuiting, and transistors Q4 and Q5 for setting voltage level. The bit lines are provided two pieces at each bit. Between the MOS transistors Q1, Q2 for pre-charge and the bit lines driving power supply terminal Vcc, three pieces of the fuses F1-F3 are connected at each column. When the leak defect occurs to the bit lines, all of the fuses F1-F3 connected to the bit lines are cut. Further, a semiconductor memory device includes a plurality of section regions, a redundancy circuit RD1 which replaces a defective cell at each section region, a redundancy circuit RD2 which replaces the defective cell at each row address. The section regions are provided at each address in the column direction. In each section region, cell ground power supply lines Vss are formed circularly.