Abstract: A method for manufacturing a semiconductor integrated circuit device includes the step of forming an SOI device region and a bulk device region on an SOI type semiconductor wafer. The method includes: removing a BOX layer and an SOI layer in a bulk device region; and thereafter forming an STI region in both the SOI device region and the bulk device region. In the method, the STI region in the SOI device region is formed to extend through the BOX layer.

Abstract: The present invention improves the production yield of a semiconductor device having nonvolatile memory cells of a split gate structure. The level difference of a lower layer resist film with which an end of a memory mat is covered is gentled, the uniformity of the thickness of a resist intermediate layer formed over the lower layer resist film is improved, and local thickness reduction or disappearance is prevented by, after forming a silicon oxide film and a silicon nitride film over each of selective gate electrodes formed in a memory cell region of a semiconductor substrate, removing the silicon oxide film and the silicon nitride film over the selective gate electrode located on the outermost side (a dummy cell region) of the memory mat in the gate length direction.

Abstract: A semiconductor device manufacturing method which eliminates the possibility that when a film is processed several times, a thin photoresist film is made over a pattern used as an alignment mark, etc. and the pattern is exposed from the photoresist film and removed in a processing step, in order to improve the reliability of a semiconductor device. Patterns used as alignment marks, etc. are linear trenches as openings in a conductive film made over a semiconductor substrate, thereby preventing the photoresist film over the conductive film from flowing toward the openings in the conductive film.

Abstract: A method for manufacturing a semiconductor integrated circuit device includes the step of forming an SOI device region and a bulk device region on an SOI type semiconductor wafer. The method includes: removing a BOX layer and an SOI layer in a bulk device region; and thereafter forming an STI region in both the SOI device region and the bulk device region. In the method, the STI region in the SOI device region is formed to extend through the BOX layer.

Abstract: The present invention improves the production yield of a semiconductor device having nonvolatile memory cells of a split gate structure. The level difference of a lower layer resist film with which an end of a memory mat is covered is gentled, the uniformity of the thickness of a resist intermediate layer formed over the lower layer resist film is improved, and local thickness reduction or disappearance is prevented by, after forming a silicon oxide film and a silicon nitride film over each of selective gate electrodes formed in a memory cell region of a semiconductor substrate, removing the silicon oxide film and the silicon nitride film over the selective gate electrode located on the outermost side (a dummy cell region) of the memory mat in the gate length direction.

Abstract: A multilayer structure which provides for optimization of a configuration of a patterned photoresist is designed. A multilayer structure (20) includes polysilicon (10), a silicon oxide film (11) and an anti-reflective film (12) which are deposited sequentially in the order noted, and a photoresist (13) is provided on the anti-reflective film (12), so that light for exposure is incident on the multilayer structure (20) through the photoresist (13). First, as a step (i), a range of thickness of the silicon oxide film (11) is determined so as to allow an absolute value of a reflection coefficient of the light for exposure at an interface between the anti-reflective film (12) and the photoresist (13) to be equal to or smaller than a first value. Subsequently, as a step (ii), the range of thickness of the silicon oxide film (11) determined in the step (i) is delimited so as to allow an absolute value of a phase of the reflection coefficient to be equal to or larger than a second value.

Abstract: A layout pattern generating unit within a lithography process margin evaluating apparatus generates a plurality of design layout patterns, using an analysis condition and information stored in a layout pattern template holding unit. In addition, a simulation condition generating unit generates a plurality of simulation conditions, using the analysis condition and information stored in a simulation condition template holding unit. A simulation unit generates a plurality of actual layout patterns, using a generated condition. Thus, the lithography process margin evaluating apparatus can reduce operational burden and improve accuracy.

Abstract: An exposure condition determination system and method, including a database configured to store a first information about a past exposure; and an exposure condition determination unit configured to determine an exposure condition suitable for a new mask which is newly made, based on said first information stored in said database and a second information about an exposure using said new mask. The first information includes at least one of a) a first mask information about properties of a mask used in said pas exposure; b) a first resist process information about properties of a resist process employed in said past exposure; c) an exposure condition information about an exposure condition employed in said past exposure; and d) a first aligner information about properties of an aligner.

Abstract: A layout pattern generating unit within a lithography process margin evaluating apparatus generates a plurality of design layout patterns, using an analysis condition and information stored in a layout pattern template holding unit. In addition, a simulation condition generating unit generates a plurality of simulation conditions, using the analysis condition and information stored in a simulation condition template holding unit. A simulation unit generates a plurality of actual layout patterns, using a generated condition. Thus, the lithography process margin evaluating apparatus can reduce operational burden and improve accuracy.

Abstract: A multilayer structure which provides for optimization of a configuration of a patterned photoresist is designed. A multilayer structure (20) includes polysilicon (10), a silicon oxide film (11) and an anti-reflective film (12) which are deposited sequentially in the order noted, and a photoresist (13) is provided on the anti-reflective film (12), so that light for exposure is incident on the multilayer structure (20) through the photoresist (13). First, as a step (i), a range of thickness of the silicon oxide film (11) is determined so as to allow an absolute value of a reflection coefficient of the light for exposure at an interface between the anti-reflective film (12) and the photoresist (13) to be equal to or smaller than a first value. Subsequently, as a step (ii), the range of thickness of the silicon oxide film (11) determined in the step (i) is delimited so as to allow an absolute value of a phase of the reflection coefficient to be equal to or larger than a second value.

Abstract: To obtain an exposure condition determined in accordance with properties of each aligner without performing complicated processes for verification of the exposure condition, a database 10 included in an exposure condition determination system 100 stores information about exposures performed in the past. Specifically, the database 10 stores mask information 11, aligner information 12, resist process information 13 and past exposure condition information 14. An exposure condition determination unit 15 determines an exposure condition suitable for a new mask in accordance with an exposure condition determination program, based on various information extracted from the database 10 and information about the new mask. Then, the exposure condition determination unit 15 outputs an exposure condition 21 for the new mask resulted from the determination.

Abstract: A layout pattern generating unit within a lithography process margin evaluating apparatus generates a plurality of design layout patterns, using an analysis condition and information stored in a layout pattern template holding unit. In addition, a simulation condition generating unit generates a plurality of simulation conditions, using the analysis condition and information stored in a simulation condition template holding unit. A simulation unit generates a plurality of actual layout patterns, using a generated condition. Thus, the lithography process margin evaluating apparatus can reduce operational burden and improve accuracy.

Abstract: In accordance with a phase shift mask of attenuation type and a manufacturing method thereof, at a prescribed region of a phase shifter portion near and around a light transmitting portion, an auxiliary pattern is provided for controlling an amount of exposure light onto a portion of an exposed material corresponding to this region. Auxiliary pattern enables to cancel light intensity of a side lobe, thereby preventing generation of a region having a high light intensity (a side lobe) at the periphery of the light transmitting portion of the phase shift mask of attenuation type.

Abstract: A photoresist mask for use in a photolithographic process for fabricating semiconductor devices. The photo mask including a transparent substrate, and at least two light blocking regions. The at least two light blocking regions are separated by a first opening and arranged at a first pitch P.sub.1 satisfying the following relationship on a main surface of the transparent substrate in a first direction:P.sub.1 >2.lambda./NA (1+.sigma.)where .lambda. represents a wavelength of exposure light in an exposure system, NA represents a numerical aperture of the exposure system and C represents coherency of the exposure light. The at least two light blocking regions are formed with second openings at second pitches smaller than the first pitch in the first direction and the second openings have the exposure light transmitting therethrough, which has a weaker intensity than the exposure light transmitting through the first opening.

Abstract: A pattern determination method includes a step for setting an interconnection width and the like, a step for representing the mask pattern and aperture configuration in functions, steps for calculating amplitude distribution of exposure light, a step for calculating intensity distribution of exposure light at an image plane, steps for calculating maximum, minimum, and reference intensity of exposure light, a step for determining exposure margin and focus margin, a step for storing data of qualification/disqualification of optical image formation, and a step for providing a display of a table. A configuration including four openings is set for the aperture. Determination of whether an optical image of an interconnection pattern can be formed or not is facilitated by the table in setting the interconnection pattern of a semiconductor device.

Abstract: An exposure mask has a predetermined principal pattern formed on a principal surface of a mask substrate and including a continuous pattern of lines which are repeatedly arranged at a first interval and an isolated pattern which is arranged adjacent to a line of the continuous pattern at a second interval greater than the first interval; and an auxiliary pattern formed along a direction in which the predetermined principal pattern is arranged, adapted to overcome multiple-beam-flux interference of diffracted light on a pupil's plane by providing the isolated pattern with cyclicity, and having a line width which falls outside a limit of resolution on a plane of projection of exposing light. Also disclosed are a method of fabricating the mask, and a method of manufacturing semiconductor devices using the mask.

Abstract: According to a method of correcting light proximity effect, a decision distance from one exposure point to the other exposure point, where influence of the light proximity effect appears, as well as a reference area ratio for deciding as to whether the light proximity effect correction is necessary or not are determined based on an optical condition of an exposure apparatus having a photomask attached thereto. Respective sides of a photomask pattern are divided into portions each having at most a prescribed length, and a ratio of an area occupied by the photomask pattern to an area of a circle having a middle point of each divided side as a center and the decision distance as a radius is determined for each of the divided sides. Comparing the area ratio for each of the divided sides with the reference area ratio for decision, a decision is made for each divided side as to whether the light proximity effect correction is necessary or not.