Abstract: Provided is efficiently performing DMA transfer of data without causing heavy overhead to occur. A data transfer detecting portion detects data transfer from an external device to a predetermined memory area in a memory; and a DMA execution instructing portion instructs, when the data transfer to the memory area is detected by the data transfer detecting portion, an image processing DMA controller to start execution of the direct memory access transfer of data from the above memory area to an image processing dedicated memory.

Abstract: A data storage controlling device including: a data dividing section for dividing target data made by a set of elements, each element being expressed in multiple values, into groups of partial data made by a set of elements, each element being expressed in two values, or dividing target data made by a set of elements, each element being expressed in two values, to partial data made by a subset of the elements; a compression section for generating compressed data blocks by means of reversibly compressing the partial data and of dividing the compressed data into predetermined size of blocks; an identifier assigning section for assigning an identifier for identifying partial data from which the compressed data block is generated to each compressed data block; and a storage processing section for reserving a storage area being smaller than the size of the target data and being common to the partial data and storing the generated compressed data block into the storage area.

Abstract: An image data processing circuit including: an input section for inputting image data; a plurality of compressing sections which are capable of compressing the input image data solely or in parallel; a plurality of decompressing sections which are capable of decompressing the compressed image data solely or in parallel; an output section for outputting the decompressed image data; a transferring section for transferring image data between a memory and of the input section, the compressing sections, the decompressing sections and the output section individually; and a transfer controlling section for selecting a mode from a parallel input/output mode, a parallel input mode and a parallel output mode.

Abstract: A data storage controlling device including: a data dividing section for dividing target data made by a set of elements, each element being expressed in multiple values, into groups of partial data made by a set of elements, each element being expressed in two values, or dividing target data made by a set of elements, each element being expressed in two values, to partial data made by a subset of the elements; a compression section for generating compressed data blocks by means of reversibly compressing the partial data and of dividing the compressed data into predetermined size of blocks; an identifier assigning section for assigning an identifier for identifying partial data from which the compressed data block is generated to each compressed data block; and a storage processing section for reserving a storage area being smaller than the size of the target data and being common to the partial data and storing the generated compressed data block into the storage area.

Abstract: An image data processing circuit including: an input section for inputting image data; a plurality of compressing sections which are capable of compressing the input image data solely or in parallel; a plurality of decompressing sections which are capable of decompressing the compressed image data solely or in parallel; an output section for outputting the decompressed image data; a transferring section for transferring image data between a memory and of the input section, the compressing sections, the decompressing sections and the output section individually; and a transfer controlling section for selecting a mode from a parallel input/output mode, a parallel input mode and a parallel output mode.