Abstract: A semiconductor integrated circuit, which operates in accordance with a power supply voltage and an external clock signal and includes a memory circuit, includes a control circuit, and first and second internal circuits. The control circuit controls the memory circuit in accordance with the power supply voltage. The first internal circuit generates an internal power supply voltage for the control circuit. The second internal circuit generates an internal clock signal for the control circuit. The semiconductor integrated circuit further includes first and second power-on reset circuits. The first power-on reset circuit generates a first power-on reset signal for the first internal circuit after the power supply voltage is generated. The second power-on reset circuit generates a second power-on reset signal for the control circuit. The second power-on reset signal is input to the control circuit after the internal clock signal is input to the control circuit.

Abstract: A semiconductor integrated circuit, which operates in accordance with a power supply voltage and an external clock signal and includes a memory circuit, includes a control circuit, and first and second internal circuits. The control circuit controls the memory circuit in accordance with the power supply voltage. The first internal circuit generates an internal power supply voltage for the control circuit. The second internal circuit generates an internal clock signal for the control circuit. The semiconductor integrated circuit further includes first and second power-on reset circuits. The first power-on reset circuit generates a first power-on reset signal for the first internal circuit after the power supply voltage is generated. The second power-on reset circuit generates a second power-on reset signal for the control circuit. The second power-on reset signal is input to the control circuit after the internal clock signal is input to the control circuit.

Abstract: A semiconductor integrated circuit, which operates in accordance with a power supply voltage and an external clock signal and includes a memory circuit, includes a control circuit, and first and second internal circuits. The control circuit controls the memory circuit in accordance with the power supply voltage. The first internal circuit generates an internal power supply voltage for the control circuit. The second internal circuit generates an internal clock signal for the control circuit. The semiconductor integrated circuit further includes first and second power-on reset circuits. The first power-on reset circuit generates a first power-on reset signal for the first internal circuit after the power supply voltage is generated. The second power-on reset circuit generates a second power-on reset signal for the control circuit. The second power-on reset signal is input to the control circuit after the internal clock signal is input to the control circuit.

Abstract: A semiconductor memory device includes a pair of bit lines; a first sense amplifier coupled to the pair of bit lines; and a first controller, which controls the first sense amplifier. The first sense amplifier includes a flip-flop circuit having a pair of NMOS transistors and a pair of PMOS transistors; a first transistor connected to a source terminal of the NMOS transistors in the flip-flop circuit; and a second transistor connected to a source terminal of the PMOS transistors in the flip-flop circuit. The first controller includes a first NOR circuit, having input terminals to which a write command signal and a sense amplifier driving signal are supplied and having an output terminal connected to a gate of the first transistor.

Abstract: An arbiter circuit minimizes the occurrence of malfunctions and permits easy adjustment. The arbiter circuit includes a data transfer request signal holding device for accepting a plurality of data transfer request signals and holding the data transfer request signals in response to predetermined timing signals, a prioritizing device for determining only a signal with the highest priority at a certain point as a valid signal and the signals with lower priorities as invalid signals in order to assign priorities to output signals from the data transfer request signal holding device, and a delaying device for generating data transfer execution signals from the output signals of the prioritizing device. This arrangement restrains the occurrence of errors in assigning priorities to data transfer request signals and permits easy priority timing setting, thus allowing easy adjustment of a circuit to be achieved.

Abstract: A semiconductor memory device includes: a pair of bit lines; a first sense amplifier coupled to the pair of bit lines; and a first controller, which controls the first sense amplifier. The first sense amplifier comprises a flip-flop circuit having a pair of NMOS transistors and a pair of PMOS transistors; a first transistor connected to a source terminal of the NMOS transistors in the flip-flop circuit; and a second transistor connected to a source terminal of the PMOS transistors in the flip-flop circuit. The first controller comprises a first NOR circuit, comprising input terminals to which a write command signal and a sense amplifier driving signal are supplied and an output terminal connected to a gate of the first transistor.

Abstract: A new and improved semiconductor memory that facilitates machining of iterated circuits and solves the problems of the prior art such as the lengthy machining process, the compromised machining accuracy and the considerable time required for device evaluation is provided. A semiconductor memory 10 is provided with a plurality of output circuits 11 and a fuse circuit 12 connected to each of the output circuits. The fuse circuit outputs output signals N1 and N2 to the individual output circuits, the signal levels of which are fixed to either H level or L level depending upon whether or not fuses f1 and f2 in the fuse circuit are disconnected. The output circuits are each provided with an output buffer circuit unit 112 and a pre-driver circuit unit 111 that drives the output buffer circuit unit. The driving capability of the pre-driver circuit unit is determined by the output signal from the fuse circuit.