Patents by Inventor AKIHIRO NISHIGAKI

AKIHIRO NISHIGAKI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11183990
    Abstract: A clock synchronization signal generator generates a dead time in which gates of both of two switching elements included in a switching circuit are in an off state, and generates the dead time for controlling a plurality of pulses having different widths to pulses having a constant width, which is output by the switching circuit.
    Type: Grant
    Filed: June 22, 2018
    Date of Patent: November 23, 2021
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Tsuyoshi Nakahira, Akihiro Nishigaki
  • Patent number: 11088662
    Abstract: A digital amplifier that minimizes and restricts an analog signal system and uses a feedback signal and a dither signal is achieved. A pulse width modulator that adjusts a pulse width of a digital signal, a switching circuit that amplifies an output signal from the pulse width modulator, and a feedback signal generation unit that generates a feedback signal based on an output signal from the switching circuit are included, the pulse width modulator adjusts the pulse width of the digital signal with reference to the feedback signal, and the feedback signal generation unit includes a first amplifier that outputs a first amplified signal in which a difference between the output signal from the switching circuit and one of a reference voltage and a dither signal is amplified and a second amplifier that amplifies a difference between the first amplified signal and the other of the dither signal and the reference voltage and outputs the amplified difference as the feedback signal.
    Type: Grant
    Filed: June 20, 2018
    Date of Patent: August 10, 2021
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Tsuyoshi Nakahira, Akihiro Nishigaki
  • Patent number: 10848144
    Abstract: A switching control circuit that controls on/off of a switching element is provided to efficiently disperse EMI noise due to high-speed switching, the switching control circuit includes a gate driver, a variable capacitance element connected to a gate of the switching element, and a capacitance changing circuit that randomly changes a capacitance of the variable capacitance element.
    Type: Grant
    Filed: November 26, 2019
    Date of Patent: November 24, 2020
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Akihiro Nishigaki, Koichiro Fujita, Kenichi Tanaka, Tsuyoshi Nakahira
  • Publication number: 20200220527
    Abstract: A clock synchronization signal generator generates a dead time in which gates of both of two switching elements included in a switching circuit are in an off state, and generates the dead time for controlling a plurality of pulses having different widths to pulses having a constant width, which is output by the switching circuit.
    Type: Application
    Filed: June 22, 2018
    Publication date: July 9, 2020
    Inventors: TSUYOSHI NAKAHIRA, AKIHIRO NISHIGAKI
  • Publication number: 20200177175
    Abstract: [Object] To efficiently disperse EMI noise due to high-speed switching. [Solution] A switching control circuit that controls on/off of a switching element comprises a gate driver, a variable capacitance element connected to a gate of the switching element, and a capacitance changing circuit that randomly changes a capacitance of the variable capacitance element.
    Type: Application
    Filed: November 26, 2019
    Publication date: June 4, 2020
    Inventors: AKIHIRO NISHIGAKI, KOICHIRO FUJITA, KENICHI TANAKA, TSUYOSHI NAKAHIRA
  • Patent number: 10673392
    Abstract: A digital amplifier includes a pulse-width adjustment circuit that adjusts the pulse width of a digital signal, a switching circuit that amplifies the output signal of the pulse-width adjustment circuit, and a feedback signal generator that generates a feedback signal based on the output signal of the switching circuit.
    Type: Grant
    Filed: January 23, 2017
    Date of Patent: June 2, 2020
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Tsuyoshi Nakahira, Akihiro Nishigaki
  • Publication number: 20200153396
    Abstract: A digital amplifier that minimizes and restricts an analog signal system and uses a feedback signal and a dither signal is achieved. A pulse width modulator that adjusts a pulse width of a digital signal, a switching circuit that amplifies an output signal from the pulse width modulator, and a feedback signal generation unit that generates a feedback signal based on an output signal from the switching circuit are included, the pulse width modulator adjusts the pulse width of the digital signal with reference to the feedback signal, and the feedback signal generation unit includes a first amplifier that outputs a first amplified signal in which a difference between the output signal from the switching circuit and one of a reference voltage and a dither signal is amplified and a second amplifier that amplifies a difference between the first amplified signal and the other of the dither signal and the reference voltage and outputs the amplified difference as the feedback signal.
    Type: Application
    Filed: June 20, 2018
    Publication date: May 14, 2020
    Inventors: TSUYOSHI NAKAHIRA, AKIHIRO NISHIGAKI
  • Publication number: 20190296696
    Abstract: A digital amplifier includes a pulse-width adjustment circuit that adjusts the pulse width of a digital signal, a switching circuit that amplifies the output signal of the pulse-width adjustment circuit, and a feedback signal generator that generates a feedback signal based on the output signal of the switching circuit.
    Type: Application
    Filed: January 23, 2017
    Publication date: September 26, 2019
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: TSUYOSHI NAKAHIRA, AKIHIRO NISHIGAKI