Abstract: A semiconductor device of the present invention includes a semiconductor layer, a low withstand voltage transistor, and a high withstand voltage transistor. In the low withstand voltage transistor, a first high concentration collector region and a first base region contact with a first low concentration collector region provided in the semiconductor layer. In the high withstand voltage transistor, a second high concentration collector region and a second base region contact a second low concentration collector region provided in the semiconductor layer. Further, the second high concentration collector region and the second base region are configured such that the distance between the second high concentration collector region and the second base region in a parallel direction to a main surface of the semiconductor layer is longer than the distance between the first high concentration collector region and the first base region.

Abstract: A semiconductor device composed of analog circuits operated by multiple power supplies is provided with a structure which enables to reduce cross talk sufficiently. In the present semiconductor device, first and second transistors formed on the p-type silicon substrate are surrounded by third and fourth high concentration n-type buried layers extending beyond two trenches provided so as to separately surround the first and second transistors. An n-type layer is formed on these high concentration n-type layers, and first and second electrodes are formed on the n-type layer. Electric potentials of the third and fourth high concentration n-type layers are stabilized at a fixed value by the supply of power through the electrodes mounted on the these layers in order to prevent cross talk.

Abstract: An active pull-down emitter coupled logic circuit includes a high voltage line, a low voltage line, a first constant current circuit coupled to the low voltage line, first and second main current paths extending between the high voltage line and the first constant current circuit, and first and second subordinate current paths extending between the high voltage line and the first constant current circuit. The subordinate current paths are paired with their respective ones of the main current paths.