Abstract: An image forming apparatus includes a supporting member extended between the first and the second frames and supporting an exposure unit, wherein the primary resonance frequency of the supporting member is higher than that of a mirror provided in the exposure unit, whereby the supporting member is prevented from being caused to resonate by oscillation generated in the driving system of the apparatus main body to thereby prevent the mirror from oscillating.

Abstract: A game system includes: a display device for displaying pictures; an input device for receiving input by a game-player and outputting a signal corresponding to the input; and a control device for controlling progress of a fishing game with referring to the signal outputted by the input device and displaying pictures corresponding to the progress of the game on the display device.

Abstract: A SRAM of complete CMOS type having its memory cell composed of six MISFETs, in which a pair of local wiring lines for connecting the input/output terminals of CMOS inverters are formed of a refractory metal silicide layer formed over a first conducting layer constituting the individual gate electrodes of the drive MISFETs, the transfer MISFETs and the load MISFETs of the memory cell and in which a reference voltage line formed over the local wiring lines is arranged to be superposed over the local wiring lines to form a capacity element.

Abstract: A SRAM of complete CMOS type having its memory cell composed of six MISFETs, in which a pair of local wiring lines for connecting the input/output terminals of CMOS inverters are formed of a refractory metal silicide layer formed over a first conducting layer constituting the individual gate electrodes of the drive MISFETs, the transfer MISFETs and the load MISFETs of the memory cell and in which a reference voltage line formed over the local wiring lines is arranged to be superposed over the local wiring lines to form a capacity element. Moreover, the capacity element is formed between the local wiring lines and the first conducting layer by superposing the local wiring lines over the first conducting layer. Moreover, the local wiring lines are formed by using resistance lowering means such as silicification. In addition, there are made common the means for lowering the resistance of the gate electrode of the transfer MISFETs and the means for forming the local wiring lines.

Abstract: A driving game machine provided with a road data memory for storing coordinate data of a road set in a game space, a player's car controller for controlling the running of a player's car on the road according to a player's operation, and a display processor for displaying an image within a field of view set in advance. The road has a start point and a goal point, a running course from the start point to the goal point has a plurality of branched roads in its intermediate positions. The player's car controller causes the player's car to run in a direction selected at each branching point in accordance with a player's operation. This makes it possible for a player to freely choose the course while competing with his rivals.

Abstract: A user sets n=0, his mail account A and password S, then computes V.sub.0 =E(A,S), W.sub.0 =E(A,V.sub.0), V.sub.1 =E(A,A.sym.1), W.sub.1 =E(A,V.sub.1) and M.sub.0 =E(W.sub.1, V.sub.0), and initially registers W.sub.0, W.sub.1, M.sub.0 and A by e-mail in a mail server. At a visiting site the user sends a service request and A to the mail server form an arbitrary terminal connected to the Internet, and the mail server reads out the authentication session number n corresponding to the identifier A and sends it back to the user. The user computes V.sub.n-1 =E(A,S.sym.(n-1)), V.sub.n+1 =E(A,S.sym.(n+1)), W.sub.n+1 =E(A,V.sub.n+1). V.sub.n =E(A,S.sym.n) and M.sub.n =E(W.sub.n+1, V.sub.n) and sends V.sub.n-1, W.sub.n+1 and M.sub.n to the mail server. The mail server computes E(A,V.sub.n-1) and E(W.sub.n, V.sub.n-1) and if they agree with preregistered W.sub.n-1 and M.sub.n-1, respectively, the mail server accepts the user as valid and sends a mail message of the user.

Abstract: A SRAM of complete CMOS type having its memory cell composed of six MISFETs, in which a pair of local wiring lines for connecting the input/output terminals of CMOS inverters are formed of a refractory metal silicide layer formed over a first conducting layer constituting the individual gate electrodes of the drive MISFETs, the transfer MISFETs and the load MISFETs of the memory cell and in which a reference voltage line formed over the local wiring lines is arranged to be superposed over the local wiring lines to form a capacity element. Moreover, the capacity element is formed between the local wiring lines and the first conducting layer by superposing the local wiring lines over the first conducting layer. Moreover, the local wiring lines are formed by using resistance lowering means such as silicification. In addition, there are made common the means for lowering the resistance of the gate electrode of the transfer MISFETs and the means for forming the local wiring lines.

Abstract: A SRAM of complete CMOS type having its memory cell composed of six MISFETs, in which a pair of local wiring lines for connecting the input/output terminals of CMOS inverters are formed of a refractory metal silicide layer formed over a first conducting layer constituting the individual gate electrodes of the drive MISFETs, the transfer MISFETs and the load MISFETs of the memory cell and in which a reference voltage line formed over the local wiring lines is arranged to be superposed over the local wiring lines to form a capacitor. The capacitor is formed between the local wiring lines and the first conducting layer by superposing the local wiring lines over the first conducting layer. Moreover, the local wiring lines are formed by using a structure with decreased resistance such as silicided structure. In addition, there are made common the processing for lowering the resistance of the gate electrode of the transfer MISFETs and the processing for forming the local wiring lines.

Abstract: The apparatus for cooling intake air includes a heat exchanger for transmitting the cold energy of fuel to a heat medium through an intermediate heat medium having a different property from the heat medium, a pressure controller for controlling the pressure within the heat exchanger so that a temperature of the intermediate heat medium is kept higher than a solidifying point of the heat medium, and an intake air cooling system for cooling intake air to be introduced into the gas turbine using the heat medium cold energy. The intermediate heat medium may be condensable by the cold energy of the fuel and vaporizable by the heat medium or may have a solidifying point lower than the fuel.

Abstract: Disclosed is a semiconductor integrated circuit device having a plurality of fine memory devices and its fabrication method, and particularly to a semiconductor integrated circuit device capable of suppressing the kink current disturbance of MOS transistors without reducing the junction characteristic of the diffusion layers and its fabrication method. In this device, an angle between the lower surface of each edge of a field oxide formed in an environmental device area, i.e. a peripheral circuit area, and the main surface of a semiconductor substrate is smaller than an angle between the lower surface of each edge of a field oxide formed in a memory cell area and the main surface of the semiconductor substrate.

Abstract: A fuel oil composition for use in a spark ignition engine, which comprises conventional gasoline for spark ignition engine use and a compound selected from the group consisting of an alkynyl alcohol, alkynyl ether, alkynyl ketone, alkenyl aldehyde or an acetal thereof, furan or a furan compound, and an alkenyl ether.

Abstract: There is provided a technique capable of reducing the electrode resistance by widening the effective area of an electrode in a cell for a standard potential supply connected to the memory cell. There is also provided a technique capable of reducing the memory cell area by reducing the area necessary for separation between the electrode in a cell for the standard potential supply and adjacent other electrodes. Two transfer MOS transistors of a first conductivity type and two driver MOS transistors are provided. A conductive layer for fixing the source potential of the driver MOS transistors to standard potential is so disposed above the transfer and driver MOS transistors as to the wholly cover the memory cell. Separation is carried out by using a photo-mask having an optically transparent substrate provided within the same transmissive portion with a pattern of a plurality of so-called phase shifter regions for inversion of the phase of transmitting light.

Abstract: In order to obtain a highly stable SRAM cell having a small cell area, a cell ratio R is set to be R=(W.sub.DEFF /L.sub.DEFF)/(W.sub.TEFF /L.sub.TEFF)<3 where L.sub.DEFF and W.sub.DEFF denote an effective channel length and an effective channel width of two driver MOSFETs 3 and 4 respectively, and L.sub.TEFF and W.sub.TEFF denote an effective channel length and an effective channel width of two transfer MOSFETs 5 and 6 respectively. Further, a maximum current I.sub.R flowing into the active loads MOSFETs 1 and 2 is set to be greater than a current I.sub.L (1.times.10.sup.-8 A) that flows into the driver MOSFET 5 when a threshold voltage is applied across the gate and the cource of the MOSFET 5. The pair of active load MOSFETs 1 and 2 are stacked on the driver MOSFETs 3 and 4 and on the transfer MOSFETs 5 and 6.

Abstract: A semiconductor static random access memory having a high .alpha.-ray immunity and a high packing density is provided which is also capable of high-speed operation. A semiconductor memory device comprises static random access memory cells each including a flip-flop circuit. Storage nodes of each flip-flop circuit have respective pn-junctions formed at regions sandwiched between gate electrodes of first insulated gate field effect transistors and gate electrodes of second insulated gate field effect transistors, respectively. The pn-junction has an area smaller than that of a channel portion of the first or second insulated gate field effect transistor.

Abstract: An apparatus for heat recovery from an exhaust gas with waste heat from a heat machinery unit, which comprises a pair of first and second chemical heat-storing units, each comprising a vessel containing a reactant material capable of releasing a reaction-susceptible material upon heating with an exhaust gas and emitting the heat of reaction upon combination with the reaction-susceptible material and a heat exchanger piping provided in the vessel and through which a heat transfer medium is passed. The high temperature gas from the heat machinery unit is applied to the vessel in one of the first and second chemical heat-storing units, thereby resulting in a reaction for leasing the reaction-susceptible material.

Abstract: Input data is split by a splitting part into a plurality of block data having an equal data length to be processed through respective channels. Each channel data is subjected in a function operation part to a function operation in direct or indirect relation to all the other channel data to produce new channel data. Each channel data is subjected in a transform operation part to a transform operation to produce new channel data. All final channel data obtained after function and transform operations are combined by a combining part to obtain randomized data.

Abstract: In a 3-transistor random access memory for dynamic operation, the invention discloses a structure in which one of the transistors is stacked on the other transistor. A transistor for writing is disposed on a transistor for reading, and one of its terminals is used in common with the gate electrode of a transistor for judging data. The other terminal is connected to one of the terminals of the transistor for reading.A memory cell capable of extremely large scale integration can be obtained.