Abstract: A booster circuit device comprises: a liquid crystal drive circuit (14) whose dissipated current changes; a timing circuit (11) for outputting a select signal according to the dissipated current of the liquid crystal drive circuit; a drive signal select circuit (12) for selecting and outputting any one of at least two drive signals CLK of different frequencies on the basis of the select signal outputted by the timing circuit (11); and a booster circuit (13) for supplying a supply voltage to the liquid crystal drive circuit (14) on the basis of the drive signal CLK outputted by the drive signal select circuit (12). Since any of the drive signals CLK of different frequencies can be selected and applied to the booster circuit (13) according to the dissipated current of the liquid crystal drive circuit (14), it is possible to reduce the current dissipation of the booster circuit, that is the current dissipation of the whole booster circuit device can be reduced markedly.

Abstract: A P-well region is provided in a semiconductor substrate of N-type. A P-channel MOSFET is arranged in the N-type substrate while an N-channel MOSFET is arranged in the P-well region. The drain regions of the respective MOSFETs consist of high concentration impurity diffused regions and low concentration impurity diffused regions arranged about the respective high concentration impurity diffused regions. Also, a drain electrode is provided to cover the entire of the high and low concentration impurity diffused regions.

Abstract: A sample-hold circuit comprises a large number of sample-hold elements, and a multi-stage shift register for controlling sampling timings of the sample-hold elments, including a large number of stages corresponding to respective sample-hold elements, wherein each of stages of the multi-stage shift register includes an input gate for taking a signal shifted from the preceding stage thereinto, an output gate for shifting the signal taken in by the input gate to the succeeding stage, respective sampling timings of the sample-hold elements corresponding to respective stages being determined by signals taken in between the input and output gates through the input gates at the respective stages. Waveforms of output signals from respective stages for determining the sampling timing are not affected by interstage wiring capacity.

Abstract: A semiconductor integrated circuit device configurated by using a polycell technique in which the wiring between the cell arrays is provided by two aluminum layers. The layers are insulated from each other by an insulator.

Abstract: An oscillator including a CMOS inverter, a feedback reactance connected between the input and output terminals of the CMOS inverter and a CMOS transfer gate connected as a feedback resistor between the input and output terminals of the CMOS inverter, a power source terminal section to which an external voltage is applied, and a power control unit for converting the external voltage to a first internal voltage which is supplied as a power source voltage to the CMOS inverter. The power control unit converts the external voltage to a second internal voltage independently from the first internal voltage and supplies the second internal voltage as a gate control voltage to the CMOS transfer gate.

Abstract: A constant voltage circuit comprises a capacitor connected between one end of a MOS transistor controlled by an operation-stop control signal and an output terminal of an inverter for inverting the operation-stop control signal. When, in the circuit having this arrangement, the transistor for operation-stop control is turned off and the hold mode is ended, the potential at one end of the transistor is quickly lowered to the ground potential. The result is to quicken the start of operation of the constant voltage circuit and hence the rise of the constant voltage output.

Abstract: A semiconductor integrated circuit device has cell arrays each constituted by unit cells containing functional circuits. Polysilicon wiring layers or diffusion wiring layers are formed in the wiring regions provided among the arrays. A first metal wiring layer is formed by computer-aided design above each polysilicon wiring layer or each diffusion wiring layer. An insulating layer is then formed on the first metal wiring layer. A second metal wiring layer is formed by computer-aided design above the insulating layer. A via contact hole is cut in the insulating layer. A portion of the second metal wiring layer fills up the via contact hole, whereby the second metal wiring layer is connected to the first metal wiring layer. The via contact hole is formed above each polysilicon wiring layer or each diffusion wiring layer. It may have its axis intersecting with the axis of the polysilicon or diffusion wiring layer or not intersecting therewith.