Abstract: A boost-type switching regulator includes an inductor; a rectifying element; a capacitor; a switching element; an output terminal; a detection voltage generating unit; an output voltage controlling unit; and a detection voltage level shifting unit. The detection voltage generating unit generates a detection voltage according to an output voltage. The output voltage controlling unit turns on and off the switching element to increase the output voltage when the detection voltage is smaller than a specific value, and to turn off the switching element to decrease the output voltage when the detection voltage is greater than the specific value. The detection voltage level shifting unit shifts the detection voltage so that the detection voltage during a voltage increasing period becomes greater than the detection voltage during a voltage decreasing period.

Abstract: A boost-type switching regulator includes an inductor; a rectifying element; a capacitor; a switching element; an output terminal; a detection voltage generating unit; an output voltage controlling unit; and a detection voltage level shifting unit. The detection voltage generating unit generates a detection voltage according to an output voltage. The output voltage controlling unit turns on and off the switching element to increase the output voltage when the detection voltage is smaller than a specific value, and to turn off the switching element to decrease the output voltage when the detection voltage is greater than the specific value. The detection voltage level shifting unit shifts the detection voltage so that the detection voltage during a voltage increasing period becomes greater than the detection voltage during a voltage decreasing period.

Abstract: Disclosed is an overvoltage protection circuit which includes a first terminal through which a first voltage is supplied to an internal circuit; a second terminal through which a second voltage is supplied; a rectifier having an input end connected to the first terminal and having an output end; and first-stage to n-th-stage switching elements which are connected in parallel to one another. The first-stage to n-th-stage switching elements have first to n-th controlling ends, respectively. Each of the switching elements has first and second controlled ends connected to the first terminal and the second terminal, respectively. The rectifier is configured to output a control voltage from the output end thereby to cause the first-stage to n-th-stage switching elements to be turned on, in response to receipt of an overvoltage from the first terminal.

Abstract: Disclosed is an overvoltage protection circuit which includes a first terminal through which a first voltage is supplied to an internal circuit; a second terminal through which a second voltage is supplied; a rectifier having an input end connected to the first terminal and having an output end; and first-stage to n-th-stage switching elements which are connected in parallel to one another. The first-stage to n-th-stage switching elements have first to n-th controlling ends, respectively. Each of the switching elements has first and second controlled ends connected to the first terminal and the second terminal, respectively. The rectifier is configured to output a control voltage from the output end thereby to cause the first-stage to n-th-stage switching elements to be turned on, in response to receipt of an overvoltage from the first terminal.

Abstract: A driving circuit of a display device is provided. In a first time period of a data writing period, a control section of the driving circuit effects control so as to short-circuit a first node which is set to a target gradation potential and a node (second node) adjacent to the first node, and such that a line (second line) between the second node and a hold capacitor of a pixel is connected in parallel to a line (first line) between the first node and the hold capacitor of the pixel. Further, in a second time period following the first time period, the control section controls switching element groups so as to cancel short-circuiting between the first node and the second node, and such that the second line is not connected in parallel to the first line.

Abstract: A driving circuit of a display device is provided. In a first time period of a data writing period, a control section of the driving circuit effects control so as to short-circuit a first node which is set to a target gradation potential and a node (second node) adjacent to the first node, and such that a line (second line) between the second node and a hold capacitor of a pixel is connected in parallel to a line (first line) between the first node and the hold capacitor of the pixel. Further, in a second time period following the first time period, the control section controls switching element groups so as to cancel short-circuiting between the first node and the second node, and such that the second line is not connected in parallel to the first line.

Abstract: The basic cell constituted by a semiconductor integrated circuit comprises two PMOS transistors and two NMOS transistors. By setting the gate widths of the gates of these transistors to prescribed lengths, the efficiency of use of elements within the basic cell is improved, and fine adjustment of the threshold voltage Vth and delay time Tpd becomes possible.

Abstract: The basic cell constituted by a semiconductor integrated circuit comprises two PMOS transistors and two NMOS transistors. By setting the gate widths of the gates of these transistors to prescribed lengths, the efficiency of use of elements within the basic cell is improved, and fine adjustment of the threshold voltage Vth and delay time Tpd becomes possible.

Abstract: The basic cell constituted by a semiconductor integrated circuit comprises two PMOS transistors and two NMOS transistors. By setting the gate widths of the gates of these transistors to prescribed lengths, the efficiency of use of elements within the basic cell is improved, and fine adjustment of the threshold voltage Vth and delay time Tpd becomes possible.

Abstract: The basic cell constituted by a semiconductor integrated circuit comprises two PMOS transistors and two NMOS transistors. By setting the gate widths of the gates of these transistors to prescribed lengths, the efficiency of use of elements within the basic cell is improved, and fine adjustment of the threshold voltage Vth and delay time Tpd becomes possible.

Abstract: A level shifter circuit which is small in delay in operating speed and also small in power consumption is provided. An NMOS transistor is connected to an input terminal at its source, to an output terminal at its drain, and to a 2V power supply line at its gate. A PMOS transistor is connected to a 3V power supply line at its source and to the output terminal at its drain. Another NMOS transistor is connected to a ground line at its source and to the output terminal at its drain. A control circuit made up of transistors supplies a voltage, which is inverse to the voltage of the input terminal, to the NMOS and PMOS transistors.

Abstract: The basic cell constituted by a semiconductor integrated circuit comprises two PMOS transistors and two NMOS transistors. By setting the gate widths of the gates of these transistors to prescribed lengths, the efficiency of use of elements within the basic cell is improved, and fine adjustment of the threshold voltage Vth and delay time Tpd becomes possible.

Abstract: The basic cell constituted by a semiconductor integrated circuit comprises two PMOS transistors and two NMOS transistors. By setting the gate widths of the gates of these transistors to prescribed lengths, the efficiency of use of elements within the basic cell is improved, and fine adjustment of the threshold voltage Vth and delay time Tpd becomes possible.

Abstract: The basic cell constituted by a semiconductor integrated circuit comprises two PMOS transistors and two NMOS transistors. By setting the gate widths of the gates of these transistors to prescribed lengths, the efficiency of use of elements within the basic cell is improved, and fine adjustment of the threshold voltage Vth and delay time Tpd becomes possible.

Abstract: An output circuit that outputs a voltage signal to a circuit having a power supply higher than that of the output circuit, wherein the voltage signal quickly increases to the potential level of the power supply of the output circuit. An input/output circuit includes the output circuit, and an input circuit that receives a voltage signal from a circuit having a power supply higher than that of the output circuit, and forwards the voltage signal to a circuit having a power supply identical to that of the input circuit. The potential level of the forwarded signal is the voltage of the power supply of the input circuit.

Abstract: An output buffer circuit for a logical integrated circuit in which the peak value of switching noise is small thereby reducing the possibility of malfunctions. A main driver has first and second transistors. The first transistor increases and decreases the current flowing between a signal output terminal and a first power supply line inversely depending on a first control potential. The second transistor increases and decreases the current flowing between the signal output terminal and a second power supply line depending on a second control potential. A predriver turns on the first and second transistors at a low speed and turns them off at a high speed. As the first and second transistors are turned on at a low speed, the peak value of switching noise is small.

Abstract: An input circuit of a semiconductor integrated circuit device includes a PMOS transistor P11 provided between an internal power supply VDD and a node S13; a PMOS transistor P12 which is provided between a node I/O to which a signal is input from an external circuit and the node S13, a POS transistor P15 which is provided between the node S13 and the node W11; and NMOS transistor N16 which controls the potential of the node S11 on the basis of the potential of the node I/O; and a second circuit which controls the potential of a node S14 on the basis of the potential of the node I/O.

Abstract: An output circuit for outputting a voltage signal to a circuit working with a power supply of a voltage higher than that under which the output circuits works, having an advantage that the voltage signal quickly increases to the potential level of the power supply of the output circuit, an input circuit for receiving a voltage signal from a circuit working with a power supply of a voltage higher than that under which the output circuits works and for forwarding the voltage signal to a circuit working with a power supply of a voltage identical to that under which the input circuit works, having an advantage that the potential level of the forwarded signal is the voltage of the power supply of the input circuit and the an input/output circuit having the foregoing both advantages.

Abstract: An output circuit that outputs a voltage signal to a circuit having a power supply higher than that of the output circuit, wherein the voltage signal quickly increases to the potential level of the power supply of the output circuit. An input/output circuit includes the output circuit, and an input circuit that receives a voltage signal from a circuit having a power supply higher than that of the output circuit, and forwards the voltage signal to a circuit having a power identical to that of the input circuit. The potential level of the forwarded signal is the voltage of the power supply of the input circuit.

Abstract: An input circuit of a semiconductor integrated circuit device includes a PMOS transistor P11 provided between an internal power supply VDD and a node S13; a PMOS transistor P12 which is provided between a node I/O to which a signal is input from an external circuit and the node S13, a POS transistor P15 which is provided between the node S13 and the node W11; and NMOS transistor N16 which controls the potential of the node S11 on the basis of the potential of the node I/O; and a second circuit which controls the potential of a node S14 on the basis of the potential of the node I/O.