Abstract: A liquid-cooled circuit device including: a module having a circuit element and a module base plate on surface of which the circuit element is mounted; a circuit case for accommodating the module; and a cooling liquid chamber for flowing a cooling liquid in contact with a back face of the module base plate of said module. The module base plate of the module is fitted into an opening provided in a member forming the cooling liquid chamber and welded without a gap.

Abstract: A liquid-cooled circuit device including: a module having a circuit element and a module base plate on surface of which the circuit element is mounted; a circuit case for accommodating the module; and a cooling liquid chamber for flowing a cooling liquid in contact with a back face of the module base plate of said module. The module base plate of the module is fitted into an opening provided in a member forming the cooling liquid chamber and welded without a gap.

Abstract: The present invention is a semiconductor apparatus having at least a part of a semiconductor device conjugated to a metal material for heat sink via an electric insulating material, wherein said electric insulating material is a bismuth glass layer.

Abstract: The present invention is a semiconductor apparatus having at least a part of a semiconductor device conjugated to a metal material for heat sink via an electric insulating material, wherein said electric insulating material is a bismuth glass layer.

Abstract: A semiconductor module in which a lead electrode is integrally formed with or pressed into resin separated from a resin case, and a connector securing a pad for bonding a metal wire to the lead electrode is bonded to a substrate with a power semiconductor element mounted thereon by an adhesive, and the like in a similar manner as the module case. According to the present invention, an electrode can be disposed in an appropriate position in the semiconductor module, and the scope of the free layout is enhanced.

Abstract: A power semiconductor module comprises a metal base, plural wiring substrates provided on said the base, a first wiring substrate of the wiring substrates having a power circuit portion including a power semiconductor device, and substrate containing portions having a resin portion in which one of the wiring substrates is contained. The one of the wiring substrates is positioned in self-alignment on the metal substrate on the basis of an inner wall of the resin portion of the substrate-containing portion.

Abstract: A power semiconductor module comprises a metal base, plural wiring substrates provided on said the base, a first wiring substrate of the wiring substrates having a power circuit portion including a power semiconductor device, and substrate containing portions having a resin portion in which one of the wiring substrates is contained. The one of the wiring substrates is positioned in self-alignment on the metal substrate on the basis of an inner wall of the resin portion of the substrate-containing portion.

Abstract: A power semiconductor module comprising a power semiconductor element included in a power circuit portion and mounted on a metal base, a first resin molded to the power semiconductor element, a control circuit element disposed on the first resin and included at least in a portion of the control circuit, and a control terminal connected to the power circuit portion and having an exposed portion thereof in the surface of the first resin, in which a portion of the control circuit is connected with the power circuit portion at the exposed portion of the control terminal. Accordingly, a resin mold type power semiconductor module capable of realizing a high performance of the control circuit portion at low cost can be realized.

Abstract: A semiconductor device includes a main circuit part having a semiconductor device formed on an electrode plate of a lead frame and a control circuit part having protective functions, which is integrally molded by a resin mold part into an integral mold structure.

Abstract: In order to bring a moduled power converter into less size and cost in the case of a structure having a lead-insert-case, an insulated metal circuit board and a printed circuit board, a difficulty was encountered in thinning a wiring width and an increase in pad area for each metal wire has interfered with a reduction in its size and cost.In the present invention to cope with it, a power converter is constructed by using a semiconductor module having such a structure that a metal base and lead frames are adhered to each other in a state in which an insulating adhesive sheet is interposed therebetween, a resin-molded outer package is adhered to the metal base with an adhesive or the like, and a resin sealing agent is charged into the resin-molded outer package to thereby integrally seal the resin-molded outer package and circuit parts such as semiconductor elements implemented therein, whereby a reduction in size and cost thereof is realized.

Abstract: A power semiconductor module having a power circuit unit; a metal base for sealing the bottom of the module; an insulation substrate for electrically insulating the metal base from the power circuit unit; external input and output terminals connected to the power circuit unit; a resin case in which the external input and output terminals are inserted by integral molding; and a resin encapsulant material has been improved substantially in its reliability through provision of a nut integrally molded with the resin case for fastening the external input and output terminals with a screw; a metal base inserted in the resin case by integral molding; and a recess to receive the end of the screw located immediately below the nut, the recess extending without penetrating the resin case, and the metal base extending to an area below the recess.

Abstract: The semiconductor IC device has a circuit arrangement constituted by a first CMOS logic gate having input and output terminals, and a second CMOS logic gate which performs the same logic operation as that of the first CMOS logic gate and which has an input terminal connected to the input terminal of the first CMOS logic gate. The arrangement also requires a differentiator circuit which has an input terminal thereof connected to an output terminal of the second CMOS logic gate and has an output terminal connected to the output terminal of the first CMOS logic gate. With such an arrangement, the dependency of the effective gate propagation delay time on an output load is lowered. As a result, therefore, the arrangement can be effected using a low power supply voltage while securing a high operation speed as well as a low power consumption. The CMOS logic gates can also be facilitated in combination with NPN bipolar transistors which are connected therewith in an emitter follower circuit form.

Abstract: A semiconductor integrated circuit device is divided into a plurality of blocks, which are individually equipped with signal generate units such that the signal generate units are distributed in the semiconductor integrated circuit device. The semiconductor integrated circuit device is preferably constructed to generate the pulse signal by the pulse generate units which are provided for the individual blocks, after all initial logic operations on the data and control signals have been taken. Thanks to this construction, an SRAM, for example, can have its write recovery time minimized to 0 so that it can achieve high-speed operations. Moreover, since predecoders are provided for the individual blocks, the wiring line number and area in the chip can be reduced to improve the degree of integration of the semiconductor integrated circuit device. Still moreover, signal delay and skew can be reduced in the chip so that high-speed can be achieved.

Abstract: The semiconductor IC device has a circuit arrangement in which one or more of the circuits, such as on a single substrate, include a totem-pole series connection of bipolar transistors which are driven by arrangements of complementary MOS circuits in a manner such that high-speed logic/switching operation is effected. Arrangements of circuits can also be effected in which the totem-pole series connection is constituted by a PNP transistor, on the power source terminal side, and an NPN or NMOS transistor on the ground or pull-down side thereof. With such configurations, the output signal swing at low operating voltages can be maximized while achieving the same with reduced propagation delay time and low power consumption. The device can also be implemented by circuitry employing capacitance bootstrapping effect as well as IIL (I.sup.2 L) design schemes.

Abstract: The device has, on a single substrate, plural internal circuits, plural input circuits for receiving external input signals and outputting the same to the internal circuit, and plural output circuits for receiving signals outputted from the internal circuits and externally outputting the same, in which at least one of the circuits includes a totem-pole output stage of a first NPN bipolar transistor, on the power supply terminal side, and a second NPN bipolar transistor, on the ground side; a first differentiator circuit for providing pulsing action to the base of the first NPN transistor; a pair of series-connected PMOS transistors for controllably driving the second NPN transistor; and feedback MOS transistors for quickening turn-off of the output stage transistors. The circuit can be effected with a second differentiator circuit in place of the series-connected pair of PMOS transistors.

Abstract: A semiconductor integrated circuit device includes a dielectric breakdown prevention circuit coupled to an external terminal for protecting an input stage circuit. The prevention circuit has bipolar transistors and complementary MISFETs including a first MISFET of a first conductivity type and a second MISFET of a second conductivity type. A first semiconductor region of the first conductivity type is formed by the same layer as a well region in which the second MISFET is formed. A second semiconductor region of the second conductivity type is formed in said first semiconductor region by the same layer as source and drain regions of the second MISFET. These first and second semiconductor regions form a first PN junction diode. The external terminal is electrically coupled to one end portion of said second semiconductor region.

Abstract: An improved bipolar transistor is provided which can be formed using a number of process steps which are similar to those used for forming MOSFETs. As such, the bipolar transistor is particularly useful in BiCMOS device arrangements. In accordance with one embodiment, a bipolar transistor is formed so that at least one of the emitter and collector regions has a high impurity region and a low impurity region. The collector and emitter regions of the device are formed in the base region to be spaced apart from one another, and the base electrode is arranged to cover the area of the base region between them. In an alternative embodiment, two collector regions can be provided in a base region on opposite sides of an emitter which is also formed in the base region. Two base electrodes can then be respectively provided in the areas between the two collectors and the emitter region. The bipolar transistors are particularly useful for forming a horizontal bipolar transistor structure.

Abstract: A monolithic semiconductor integrated circuit device includes bipolar transistors and MOS transistors constituting plural blocks formed in a single semiconductor substrate and capable of performing different functions. The bipolar transistors in the blocks have different breakdown voltages and different operation speeds due to the selection of different resistances of their collector regions.

Abstract: A semiconductor integrated circuit device is equipped with a DRAM whose memory cell is formed as a series circuit of a memory cell selection MISFET and a data storage capacitance element of a stacked structure. A complementary data line extends on an upper electrode layer of the data storage capacitance element of the stacked structure through an inter-level insulation film which is connected to a semiconductor region of the memory cell selection MISFET. To reduce parasitic capacitance the wiring width of the complementary data line is formed to be smaller than the film thickness of the inter-level insulation film between the complementary data line and the upper electrode layer of said data storage capacitance element of the stacked structure.