Patents by Inventor Akihiro YUU

Akihiro YUU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Transistor circuits including fringeless transistors and method of making the same
    Patent number: 12027520
    Abstract: A first field effect transistor contains a first active region including a source region, a drain region and a channel region located between the source region and the drain region, a first gate dielectric overlying the active region, and a first gate electrode overlying the first gate dielectric. A second field effect transistor contains a second active region including a source region, a drain region and a channel region located between the source region and the drain region, a second gate dielectric overlying the active region, a second gate electrode overlying the second gate dielectric. A trench isolation region surrounds the first and the second active regions. The first field effect transistor includes a fringe region in which the first gate electrode extends past the active region perpendicular to the source region to drain region direction and the second field effect transistor does not include the fringe region.
    Type: Grant
    Filed: October 14, 2021
    Date of Patent: July 2, 2024
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Akihiro Yuu, Dai Iwata, Hiroyuki Ogawa
  • TRANSISTOR CIRCUITS INCLUDING FRINGELESS TRANSISTORS AND METHOD OF MAKING THE SAME
    Publication number: 20220367449
    Abstract: A first field effect transistor contains a first active region including a source region, a drain region and a channel region located between the source region and the drain region, a first gate dielectric overlying the active region, and a first gate electrode overlying the first gate dielectric. A second field effect transistor contains a second active region including a source region, a drain region and a channel region located between the source region and the drain region, a second gate dielectric overlying the active region, a second gate electrode overlying the second gate dielectric. A trench isolation region surrounds the first and the second active regions. The first field effect transistor includes a fringe region in which the first gate electrode extends past the active region perpendicular to the source region to drain region direction and the second field effect transistor does not include the fringe region.
    Type: Application
    Filed: October 14, 2021
    Publication date: November 17, 2022
    Inventors: Akihiro YUU, Dai IWATA, Hiroyuki OGAWA