Patents by Inventor Akihisa Aoyama

Akihisa Aoyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8552946
    Abstract: In a display device and a display driver, when a grayscale of a display image is equal to or lower than a specific grayscale value obtained from a histogram of the display image, a display grayscale is extended with a linear function. On the other hand, when a grayscale of a display image is equal to or higher than the specific grayscale value, histogram equalization of a part higher than the specific grayscale value is performed, and the display grayscale is extended with a non-linear function obtained from the histogram equalization.
    Type: Grant
    Filed: April 24, 2008
    Date of Patent: October 8, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Yoshiki Kurokawa, Yukari Katayama, Hiroki Awakura, Naoki Takada, Yasuyuki Kudo, Akihito Akai, Goki Toshima, Akihisa Aoyama, Goro Sakamaki
  • Publication number: 20130044146
    Abstract: In a display device and a display driver, when a grayscale of a display image is equal to or lower than a specific grayscale value obtained from a histogram of the display image, a display grayscale is extended with a linear function. On the other hand, when a grayscale of a display image is equal to or higher than the specific grayscale value, histogram equalization of a part higher than the specific grayscale value is performed, and the display grayscale is extended with a non-linear function obtained from the histogram equalization.
    Type: Application
    Filed: October 9, 2012
    Publication date: February 21, 2013
    Inventors: Yoshiki KUROKAWA, Yukari KATAYAMA, Hiroki AWAKURA, Naoki TAKADA, Yasuyuki KUDO, Akihito AKAI, Goki TOSHIMA, Akihisa AOYAMA, Goro SAKAMAKI
  • Publication number: 20080316167
    Abstract: A display driver driving a display panel according to inputted display data comprises: a first circuit changing brightness of a display image by conversion of the display data based on a first reference value and a second reference value, the first reference value being a display data value at a first position in an upper part of a histogram of the inputted display data, and the second reference value being a display data value at a second position in a lower portion of the histogram; a second circuit changing brightness of a illuminating device illuminating the display panel based on the first reference value; and a control circuit performing a processing of making the brightness of the display image high by the first circuit and a processing of making the brightness of the illuminating device low by the second circuit in correlation with the brightness of the display image.
    Type: Application
    Filed: June 6, 2008
    Publication date: December 25, 2008
    Inventors: Yoshiki KUROKAWA, Yukari Katayama, Yasuyuki Kudo, Akihito Akai, Goki Toshima, Akihisa Aoyama
  • Publication number: 20080272999
    Abstract: In a display device and a display driver, when a grayscale of a display image is equal to or lower than a specific grayscale value obtained from a histogram of the display image, a display grayscale is extended with a linear function. On the other hand, when a grayscale of a display image is equal to or higher than the specific grayscale value, histogram equalization of a part higher than the specific grayscale value is performed, and the display grayscale is extended with a non-linear function obtained from the histogram equalization.
    Type: Application
    Filed: April 24, 2008
    Publication date: November 6, 2008
    Inventors: Yoshiki Kurokawa, Yukari Katayama, Hiroki Awakura, Naoki Takada, Yasuyuki Kudo, Akihito Akai, Goki Toshimi, Akihisa Aoyama, Goro Sakamaki
  • Patent number: 7254068
    Abstract: Parasitic capacitances formed between bit lines to which signals are to be read out of memory cells and a signal transmission line arranged above them are to be reduced. Second complementary global bit lines for transmitting data read out of memory cells MC via complementary bit lines are arranged above a memory cell array. Each second global bit line is so arranged that a triangle having as its vertexes the center of the section of one of the complementary bit lines, that of the section of the other and that of the section of the second global bit line arranged directly above these complementary bit lines be an isosceles triangle.
    Type: Grant
    Filed: March 15, 2006
    Date of Patent: August 7, 2007
    Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.
    Inventors: Hiroki Ueno, Takashi Akioka, Kinya Mitsumoto, Akihisa Aoyama, Masao Shinozaki
  • Publication number: 20060158918
    Abstract: Parasitic capacitances formed between bit lines to which signals are to be read out of memory cells and a signal transmission line arranged above them are to be reduced. Second complementary global bit lines for transmitting data read out of memory cells MC via complementary bit lines are arranged above a memory cell array. Each second global bit line is so arranged that a triangle having as its vertexes the center of the section of one of the complementary bit lines, that of the section of the other and that of the section of the second global bit line arranged directly above these complementary bit lines be an isosceles triangle.
    Type: Application
    Filed: March 15, 2006
    Publication date: July 20, 2006
    Inventors: Hiroki Ueno, Takashi Akioka, Kinya Mitsumoto, Akihisa Aoyama, Masao Shinozaki
  • Patent number: 7068551
    Abstract: Parasitic capacitances formed between bit lines to which signals are to be read out of memory cells and a signal transmission line arranged above them are to be reduced. Second complementary global bit lines for transmitting data read out of memory cells MC via complementary bit lines are arranged above a memory cell array. Each second global bit line is so arranged that a triangle having as its vertexes the center of the section of one of the complementary bit lines, that of the section of the other and that of the section of the second global bit line arranged directly above these complementary bit lines be an isosceles triangle.
    Type: Grant
    Filed: February 1, 2005
    Date of Patent: June 27, 2006
    Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.
    Inventors: Hiroki Ueno, Takashi Akioka, Kinya Mitsumoto, Akihisa Aoyama, Masao Shinozaki
  • Publication number: 20050128839
    Abstract: Parasitic capacitances formed between bit lines to which signals are to be read out of memory cells and a signal transmission line arranged above them are to be reduced. Second complementary global bit lines for transmitting data read out of memory cells MC via complementary bit lines are arranged above a memory cell array. Each second global bit line is so arranged that a triangle having as its vertexes the center of the section of one of the complementary bit lines, that of the section of the other and that of the section of the second global bit line arranged directly above these complementary bit lines be an isosceles triangle.
    Type: Application
    Filed: February 1, 2005
    Publication date: June 16, 2005
    Inventors: Hiroki Ueno, Takashi Akioka, Kinya Mitsumoto, Akihisa Aoyama, Masao Shinozaki
  • Patent number: 6856559
    Abstract: Parasitic capacitances formed between bit lines to which signals are to be read out of memory cells and a signal transmission line arranged above them are to be reduced. Second complementary global bit lines for transmitting data read out of memory cells MC via complementary bit lines are arranged above a memory cell array. Each second global bit line is so arranged that a triangle having as its vertexes the center of the section of one of the complementary bit lines, that of the section of the other and that of the section of the second global bit line arranged directly above these complementary bit lines be an isosceles triangle.
    Type: Grant
    Filed: August 11, 2003
    Date of Patent: February 15, 2005
    Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.
    Inventors: Hiroki Ueno, Takashi Akioka, Kinya Mitsumoto, Akihisa Aoyama, Masao Shinozaki
  • Publication number: 20040027896
    Abstract: Parasitic capacitances formed between bit lines to which signals are to be read out of memory cells and a signal transmission line arranged above them are to be reduced. Second complementary global bit lines for transmitting data read out of memory cells MC via complementary bit lines are arranged above a memory cell array. Each second global bit line is so arranged that a triangle having as its vertexes the center of the section of one of the complementary bit lines, that of the section of the other and that of the section of the second global bit line arranged directly above these complementary bit lines be an isosceles triangle.
    Type: Application
    Filed: August 11, 2003
    Publication date: February 12, 2004
    Applicants: Hitachi, Ltd., Hitachi ULSI Systems Co. , Ltd.
    Inventors: Hiroki Ueno, Takashi Akioka, Kinya Mitsumoto, Akihisa Aoyama, Masao Shinozaki
  • Patent number: 6625070
    Abstract: Parasitic capacitances formed between bit lines to which signals are to be read out of memory cells and a signal transmission line arranged above them are to be reduced. Second complementary global bit lines for transmitting data read out of memory cells MC via complementary bit lines are arranged above a memory cell array. Each second global bit line is so arranged that a triangle having as its vertexes the center of the section of one of the complementary bit lines, that of the section of the other and that of the section of the second global bit line arranged directly above these complementary bit lines be an isosceles triangle.
    Type: Grant
    Filed: December 11, 2001
    Date of Patent: September 23, 2003
    Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.
    Inventors: Hiroki Ueno, Takashi Akioka, Kinya Mitsumoto, Akihisa Aoyama, Masao Shinozaki
  • Publication number: 20020075732
    Abstract: Parasitic capacitances formed between bit lines to which signals are to be read out of memory cells and a signal transmission line arranged above them are to be reduced. Second complementary global bit lines for transmitting data read out of memory cells MC via complementary bit lines are arranged above a memory cell array. Each second global bit line is so arranged that a triangle having as its vertexes the center of the section of one of the complementary bit lines, that of the section of the other and that of the section of the second global bit line arranged directly above these complementary bit lines be an isosceles triangle.
    Type: Application
    Filed: December 11, 2001
    Publication date: June 20, 2002
    Applicant: Hitachi, Ltd
    Inventors: Hiroki Ueno, Takashi Akioka, Kinya Mitsumoto, Akihisa Aoyama, Masao Shinozaki