Abstract: A machine tool includes a tool rest including first holders each configured to hold a tool for an inner-diameter side and second holders each configured to hold a tool for an outer-diameter side, a machining control unit configured to control the tool rest to machine the workpiece, a tool changing unit, and a tool management unit configured to identify an unused tool. In a case where a plurality of tools of the same type are held by both the first and second holders, when the number of the first holders is larger than the number of the second holders, and one of the tools held by the second holders is identified as the unused tool, the tool changing unit changes the unused tool in the second holder with the tool in the first holder.

Abstract: The present invention includes a tool magazine (10) storing a plurality of tools (T), a turret (3) to which a plurality of tools (T) are attached, and a tool changer (20) changing a tool (T) attached to the turret (3) for a tool (T) stored in the tool magazine (10). The tool changer (20) has two tool grippers for gripping tools (T) and replaces tools (T) attached to the turret (3) with one another using the two tool grippers based on tool information stored in a tool information storage (43) under control by a tool change control unit (42).

Abstract: In a case of attaching a plurality of tools of the same type to a tool rest, machining work is continued even when a sufficient number of normal tools are not left. A machine tool includes a tool rest including a first holder for an inner-diameter side and a second holder for an outer-diameter side, a machining control unit configured to control the tool rest to machine the workpiece, a tool changing unit configured to change tools, and a tool management unit configured to identify an unused tool. In a case of attaching a plurality of tools of the same type to both the first and second holders, when the number of the first holders is larger than the number of the second holders, the tool changing unit attaches the unused tool to the first holder.

Abstract: A machine tool includes a turret including first and second stations, a tool storage unit capable of storing tools therein, a machining control unit for controlling a tool in accordance with a machining program, a tool changing unit for replacing the tool attached to the turret with a tool stored in the tool storage unit, and a tool pattern memory for memorizing, as a first tool pattern, a combination of tools at the first and second stations which is associated with a first part of the machining program and, as a second tool pattern, a combination of tools at the first and second stations which is associated with a second part of the machining program after the first part. When machining is stopped during execution of the second part, the tool changing unit changes tools in accordance with a past tool pattern saved in association with a part before stop on the machining program.

Abstract: In a display device and a display driver, when a grayscale of a display image is equal to or lower than a specific grayscale value obtained from a histogram of the display image, a display grayscale is extended with a linear function. On the other hand, when a grayscale of a display image is equal to or higher than the specific grayscale value, histogram equalization of a part higher than the specific grayscale value is performed, and the display grayscale is extended with a non-linear function obtained from the histogram equalization.

Abstract: In a display device and a display driver, when a grayscale of a display image is equal to or lower than a specific grayscale value obtained from a histogram of the display image, a display grayscale is extended with a linear function. On the other hand, when a grayscale of a display image is equal to or higher than the specific grayscale value, histogram equalization of a part higher than the specific grayscale value is performed, and the display grayscale is extended with a non-linear function obtained from the histogram equalization.

Abstract: A display driver driving a display panel according to inputted display data comprises: a first circuit changing brightness of a display image by conversion of the display data based on a first reference value and a second reference value, the first reference value being a display data value at a first position in an upper part of a histogram of the inputted display data, and the second reference value being a display data value at a second position in a lower portion of the histogram; a second circuit changing brightness of a illuminating device illuminating the display panel based on the first reference value; and a control circuit performing a processing of making the brightness of the display image high by the first circuit and a processing of making the brightness of the illuminating device low by the second circuit in correlation with the brightness of the display image.

Abstract: In a display device and a display driver, when a grayscale of a display image is equal to or lower than a specific grayscale value obtained from a histogram of the display image, a display grayscale is extended with a linear function. On the other hand, when a grayscale of a display image is equal to or higher than the specific grayscale value, histogram equalization of a part higher than the specific grayscale value is performed, and the display grayscale is extended with a non-linear function obtained from the histogram equalization.

Abstract: Parasitic capacitances formed between bit lines to which signals are to be read out of memory cells and a signal transmission line arranged above them are to be reduced. Second complementary global bit lines for transmitting data read out of memory cells MC via complementary bit lines are arranged above a memory cell array. Each second global bit line is so arranged that a triangle having as its vertexes the center of the section of one of the complementary bit lines, that of the section of the other and that of the section of the second global bit line arranged directly above these complementary bit lines be an isosceles triangle.

Abstract: Parasitic capacitances formed between bit lines to which signals are to be read out of memory cells and a signal transmission line arranged above them are to be reduced. Second complementary global bit lines for transmitting data read out of memory cells MC via complementary bit lines are arranged above a memory cell array. Each second global bit line is so arranged that a triangle having as its vertexes the center of the section of one of the complementary bit lines, that of the section of the other and that of the section of the second global bit line arranged directly above these complementary bit lines be an isosceles triangle.

Abstract: Parasitic capacitances formed between bit lines to which signals are to be read out of memory cells and a signal transmission line arranged above them are to be reduced. Second complementary global bit lines for transmitting data read out of memory cells MC via complementary bit lines are arranged above a memory cell array. Each second global bit line is so arranged that a triangle having as its vertexes the center of the section of one of the complementary bit lines, that of the section of the other and that of the section of the second global bit line arranged directly above these complementary bit lines be an isosceles triangle.

Abstract: Parasitic capacitances formed between bit lines to which signals are to be read out of memory cells and a signal transmission line arranged above them are to be reduced. Second complementary global bit lines for transmitting data read out of memory cells MC via complementary bit lines are arranged above a memory cell array. Each second global bit line is so arranged that a triangle having as its vertexes the center of the section of one of the complementary bit lines, that of the section of the other and that of the section of the second global bit line arranged directly above these complementary bit lines be an isosceles triangle.

Abstract: Parasitic capacitances formed between bit lines to which signals are to be read out of memory cells and a signal transmission line arranged above them are to be reduced. Second complementary global bit lines for transmitting data read out of memory cells MC via complementary bit lines are arranged above a memory cell array. Each second global bit line is so arranged that a triangle having as its vertexes the center of the section of one of the complementary bit lines, that of the section of the other and that of the section of the second global bit line arranged directly above these complementary bit lines be an isosceles triangle.

Abstract: Parasitic capacitances formed between bit lines to which signals are to be read out of memory cells and a signal transmission line arranged above them are to be reduced. Second complementary global bit lines for transmitting data read out of memory cells MC via complementary bit lines are arranged above a memory cell array. Each second global bit line is so arranged that a triangle having as its vertexes the center of the section of one of the complementary bit lines, that of the section of the other and that of the section of the second global bit line arranged directly above these complementary bit lines be an isosceles triangle.

Abstract: Parasitic capacitances formed between bit lines to which signals are to be read out of memory cells and a signal transmission line arranged above them are to be reduced. Second complementary global bit lines for transmitting data read out of memory cells MC via complementary bit lines are arranged above a memory cell array. Each second global bit line is so arranged that a triangle having as its vertexes the center of the section of one of the complementary bit lines, that of the section of the other and that of the section of the second global bit line arranged directly above these complementary bit lines be an isosceles triangle.

Abstract: Parasitic capacitances formed between bit lines to which signals are to be read out of memory cells and a signal transmission line arranged above them are to be reduced. Second complementary global bit lines for transmitting data read out of memory cells MC via complementary bit lines are arranged above a memory cell array. Each second global bit line is so arranged that a triangle having as its vertexes the center of the section of one of the complementary bit lines, that of the section of the other and that of the section of the second global bit line arranged directly above these complementary bit lines be an isosceles triangle.