Patents by Inventor Akihisa Iguchi

Akihisa Iguchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7164195
    Abstract: In a semiconductor device including a semiconductor wafer having a first main surface where a circuit element is formed, electrode pads are formed at an upper portion of the first main surface of the semiconductor wafer electrically connected with the circuit element. Index marks are formed on a second main surface of the semiconductor wafer that is opposite the first main surface. The index marks consist of line segments and indicate a direction along which the semiconductor device is to be mounted.
    Type: Grant
    Filed: August 31, 2004
    Date of Patent: January 16, 2007
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Yuuki Furuya, Akihisa Iguchi, Kentarou Arai
  • Publication number: 20050023706
    Abstract: In a semiconductor device including a semiconductor wafer having a first main surface where a circuit element is formed, electrode pads are formed at an upper portion of the first main surface of the semiconductor wafer electrically connected with the circuit element. Index marks are formed on a second main surface of the semiconductor wafer that is opposite the first main surface. The index marks consist of line segments and indicate a direction along which the semiconductor device is to be mounted.
    Type: Application
    Filed: August 31, 2004
    Publication date: February 3, 2005
    Inventors: Yuuki Furuya, Akihisa Iguchi, Kentarou Arai
  • Patent number: 6787892
    Abstract: In a semiconductor device including a semiconductor wafer having a main surface where a circuit element is formed, electrode pads are formed at an upper portion of the main surface of the semiconductor wafer as electrically connected with the circuit element. A sealing resin seals the upper portion of the main surface of the semiconductor wafer, and external connection terminals are formed at the upper portion of the main surface so as to project out from the surface of the sealing resin and are arrayed in a substantially regular pattern over specific intervals from one another. At least one of the external connection terminals has a shape different from the shape of the other external connection terminals. The shape of the external connection terminal is used as an index mark, so that the index mark forming process is simplified and the index mark does not come off.
    Type: Grant
    Filed: April 25, 2002
    Date of Patent: September 7, 2004
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Yuuki Furuya, Akihisa Iguchi, Kentarou Arai
  • Patent number: 6558982
    Abstract: A semiconductor device manufacturing method and a mold die that make it possible to expose the upper portions of external terminals with ease without having to implement a polishing process, are provided. The semiconductor device manufacturing method comprises a step in which external terminals are formed as bumps on a semiconductor element substrate, a step in which the semiconductor element substrate is mounted on the upper surface of a lower die of a mold die comprising an upper die and the lower die that is used to seal the semiconductor element substrate in resin, a step in which a tape is placed over the area of the upper surface of the lower die where the semiconductor element substrate is mounted and a step in which the upper die is placed in close contact with the external terminals. By employing this manufacturing method, it is possible to control the clamping force of the mold die.
    Type: Grant
    Filed: December 15, 1999
    Date of Patent: May 6, 2003
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Akihisa Iguchi
  • Publication number: 20020158326
    Abstract: In a semiconductor device comprising a semiconductor wafer 1 that includes a main surface where a circuit element is formed, a plurality of electrode pads formed at an upper portion of the main surface of the semiconductor wafer electrically connected with the circuit element, a sealing resin 3 that seals the upper portion of the main surface of the semiconductor wafer and a plurality of external connection terminals formed at the upper portion of the main surface so as to project out from the surface of the sealing resin and arrayed in a substantially regular pattern over specific intervals from one another, at least one external connection terminal among the plurality of external connection terminals is formed in a shape different from the shape of the other external connection terminals. Since the shape of the external connection terminal itself can be used as an index mark, the index mark forming process can be simplified and such an index mark does not come off the semiconductor wafer, either.
    Type: Application
    Filed: April 25, 2002
    Publication date: October 31, 2002
    Inventors: Yuuki Furuya, Akihisa Iguchi, Kentarou Arai
  • Patent number: 6396708
    Abstract: A push-back circuit board frame on which a semiconductor device is mounted, including a circuit board, the board being detached from the frame and being returned to an original position in the frame, a cavity formed at an edge of the circuit board in the frame, a semiconductor chip mounted on the circuit board, a resin sealing the semiconductor chip on the circuit board, and a support base made of the same material as the resin, formed in the cavity, where all of the resin is formed simultaneously, and connected each other.
    Type: Grant
    Filed: February 7, 2000
    Date of Patent: May 28, 2002
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Akihisa Iguchi