Patents by Inventor Akihisa Kuroyanagi
Akihisa Kuroyanagi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11195790Abstract: A fan-out semiconductor package includes: a frame including insulating layers, wiring layers, and connection via layers, and having a recess portion and a stopper layer disposed on a bottom surface of the recess portion; a semiconductor chip disposed in the recess portion; a resin layer disposed on an active surface of the semiconductor chip; an encapsulant covering at least portions of side surfaces of the semiconductor chip and the resin layer and filling at least portions of the recess portion; a first redistribution layer disposed on the resin layer and the encapsulant; first redistribution vias penetrating through the resin layer to fill via holes in the resin layer exposing at least portions of the connection pads and electrically connecting the connection pads and the first redistribution layer to each other; and a connection member disposed on the resin layer and the encapsulant and including one or more second redistribution layers.Type: GrantFiled: November 15, 2019Date of Patent: December 7, 2021Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Akihisa Kuroyanagi, Jun Woo Myung, Eun Sil Kim, Yeong A Kim
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Patent number: 10854528Abstract: A semiconductor package including an organic interposer includes: first and second semiconductor chips each having active surfaces having connection pads disposed thereon; the organic interposer disposed on the active surfaces of the first and second semiconductor chips and including a wiring layer electrically connected to the connection pads; barrier layers disposed on side surfaces of the first and second semiconductor chips; and an encapsulant encapsulating at least portions of the first and second semiconductor chips.Type: GrantFiled: January 17, 2020Date of Patent: December 1, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jun Woo Myung, Akihisa Kuroyanagi, Yeong A Kim, Eun Sil Kim
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Patent number: 10692791Abstract: An electronic component package includes a core member including an insulating layer, and having a first through-hole passing through the insulating layer, a semiconductor chip disposed in the first through-hole, and having an active surface on which a connection pad is disposed, and an inactive surface opposing the active surface, an encapsulant encapsulating the core member and the semiconductor chip, and filling at least a portion of the first through-hole, a connection member disposed on the core member and the semiconductor chip, and including a redistribution layer electrically connected to the connection pad, a backside metal layer disposed on the encapsulant, and covering at least the inactive surface of the semiconductor chip, and a backside metal via passing through the encapsulant, and connecting the backside metal layer to one side of the insulating layer. The backside metal via is in contact with the one side of the insulating layer.Type: GrantFiled: November 1, 2018Date of Patent: June 23, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Akihisa Kuroyanagi, Jun Woo Myung, Jae Kul Lee
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Publication number: 20200152538Abstract: A semiconductor package including an organic interposer includes: first and second semiconductor chips each having active surfaces having connection pads disposed thereon; the organic interposer disposed on the active surfaces of the first and second semiconductor chips and including a wiring layer electrically connected to the connection pads; barrier layers disposed onside surfaces of the first and second semiconductor chips; and an encapsulant encapsulating at least portions of the first and second semiconductor chips.Type: ApplicationFiled: January 17, 2020Publication date: May 14, 2020Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jun Woo MYUNG, Akihisa KUROYANAGI, Yeong A. KIM, Eun Sil KIM
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Publication number: 20200083163Abstract: A fan-out semiconductor package includes: a frame including insulating layers, wiring layers, and connection via layers, and having a recess portion and a stopper layer disposed on a bottom surface of the recess portion; a semiconductor chip disposed in the recess portion; a resin layer disposed on an active surface of the semiconductor chip; an encapsulant covering at least portions of side surfaces of the semiconductor chip and the resin layer and filling at least portions of the recess portion; a first redistribution layer disposed on the resin layer and the encapsulant; first redistribution vias penetrating through the resin layer to fill via holes in the resin layer exposing at least portions of the connection pads and electrically connecting the connection pads and the first redistribution layer to each other; and a connection member disposed on the resin layer and the encapsulant and including one or more second redistribution layers.Type: ApplicationFiled: November 15, 2019Publication date: March 12, 2020Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Akihisa KUROYANAGI, Jun Woo MYUNG, Eun Sil KIM, Yeong A KIM
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Patent number: 10541187Abstract: A semiconductor package including an organic interposer includes: first and second semiconductor chips each having active surfaces having connection pads disposed thereon; the organic interposer disposed on the active surfaces of the first and second semiconductor chips and including a wiring layer electrically connected to the connection pads; barrier layers disposed onside surfaces of the first and second semiconductor chips; and an encapsulant encapsulating at least portions of the first and second semiconductor chips.Type: GrantFiled: April 11, 2018Date of Patent: January 21, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jun Woo Myung, Akihisa Kuroyanagi, Yeong A Kim, Eun Sil Kim
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Patent number: 10504836Abstract: A fan-out semiconductor package includes: a frame including insulating layers, wiring layers, and connection via layers, and having a recess portion and a stopper layer disposed on a bottom surface of the recess portion; a semiconductor chip disposed in the recess portion; a resin layer disposed on an active surface of the semiconductor chip; an encapsulant covering at least portions of side surfaces of the semiconductor chip and the resin layer and filling at least portions of the recess portion; a first redistribution layer disposed on the resin layer and the encapsulant; first redistribution vias penetrating through the resin layer to fill via holes in the resin layer exposing at least portions of the connection pads and electrically connecting the connection pads and the first redistribution layer to each other; and a connection member disposed on the resin layer and the encapsulant and including one or more second redistribution layers.Type: GrantFiled: August 2, 2018Date of Patent: December 10, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Akihisa Kuroyanagi, Jun Woo Myung, Eun Sil Kim, Yeong A Kim
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Publication number: 20190371692Abstract: An electronic component package includes a core member including an insulating layer, and having a first through-hole passing through the insulating layer, a semiconductor chip disposed in the first through-hole, and having an active surface on which a connection pad is disposed, and an inactive surface opposing the active surface, an encapsulant encapsulating the core member and the semiconductor chip, and filling at least a portion of the first through-hole, a connection member disposed on the core member and the semiconductor chip, and including a redistribution layer electrically connected to the connection pad, a backside metal layer disposed on the encapsulant, and covering at least the inactive surface of the semiconductor chip, and a backside metal via passing through the encapsulant, and connecting the backside metal layer to one side of the insulating layer. The backside metal via is in contact with the one side of the insulating layer.Type: ApplicationFiled: November 1, 2018Publication date: December 5, 2019Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Akihisa KUROYANAGI, Jun Woo MYUNG, Jae Kul LEE
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Patent number: 10475776Abstract: A fan-out semiconductor package module includes a core member having first and second through-holes. A semiconductor chip is in the first through-hole and has an active surface with a connection pad and an inactive surface opposing the active surface. Another passive component is in the second through-hole. An first encapsulant covers at least portions of the core member and the passive component, and fills at least a portion of the second through-hole. A reinforcing member is on the first encapsulant. A second encapsulant covers at least a portion of the semiconductor chip, and fills at least a portion of the first through-hole. A connection member is on the core member, the active surface of the semiconductor chip, and the passive component, and includes a redistribution layer electrically connected to the connection pad and the passive component.Type: GrantFiled: February 20, 2018Date of Patent: November 12, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Yeong A Kim, Eun Sil Kim, Young Gwan Ko, Akihisa Kuroyanagi, Jin Su Kim, Jun Woo Myung
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Publication number: 20190252311Abstract: A fan-out semiconductor package includes: a frame including insulating layers, wiring layers, and connection via layers, and having a recess portion and a stopper layer disposed on a bottom surface of the recess portion; a semiconductor chip disposed in the recess portion; a resin layer disposed on an active surface of the semiconductor chip; an encapsulant covering at least portions of side surfaces of the semiconductor chip and the resin layer and filling at least portions of the recess portion; a first redistribution layer disposed on the resin layer and the encapsulant; first redistribution vias penetrating through the resin layer to fill via holes in the resin layer exposing at least portions of the connection pads and electrically connecting the connection pads and the first redistribution layer to each other; and a connection member disposed on the resin layer and the encapsulant and including one or more second redistribution layers.Type: ApplicationFiled: August 2, 2018Publication date: August 15, 2019Inventors: Akihisa KUROYANAGI, Jun Woo MYUNG, Eun Sil KIM, Yeong A KIM
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Publication number: 20190139851Abstract: A semiconductor package including an organic interposer includes: first and second semiconductor chips each having active surfaces having connection pads disposed thereon; the organic interposer disposed on the active surfaces of the first and second semiconductor chips and including a wiring layer electrically connected to the connection pads; barrier layers disposed onside surfaces of the first and second semiconductor chips; and an encapsulant encapsulating at least portions of the first and second semiconductor chips.Type: ApplicationFiled: April 11, 2018Publication date: May 9, 2019Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Jun Woo MYUNG, Akihisa KUROYANAGI, Yeong A KIM, Eun Sil KIM
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Publication number: 20190131285Abstract: A fan-out semiconductor package module includes a core member having first and second through-holes. A semiconductor chip is in the first through-hole and has an active surface with a connection pad and an inactive surface opposing the active surface. Another passive component is in the second through-hole. An first encapsulant covers at least portions of the core member and the passive component, and fills at least a portion of the second through-hole. A reinforcing member is on the first encapsulant. A second encapsulant covers at least a portion of the semiconductor chip, and fills at least a portion of the first through-hole. A connection member is on the core member, the active surface of the semiconductor chip, and the passive component, and includes a redistribution layer electrically connected to the connection pad and the passive component.Type: ApplicationFiled: February 20, 2018Publication date: May 2, 2019Inventors: Yeong A KIM, Eun Sil KIM, Young Gwan KO, Akihisa KUROYANAGI, Jin Su KIM, Jun Woo MYUNG
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Publication number: 20070049679Abstract: A fly ash powder containing substantially no silanol group, wherein electric conductivity of water extract after soaking of 10 g of the fly ash powder in 100 ml of a pure water at 20° C. for 6 hours is 200 ?S/cm or less. A fly ash powder in which the ionic impurity content is reduced and is excellent in affinity (wettability) for various resins is provided.Type: ApplicationFiled: March 11, 2004Publication date: March 1, 2007Applicant: NITTO DENKO CORPORATIONInventors: Akihisa Kuroyanagi, Shuji Nishimori, Tsuyoshi Yamaji
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Patent number: 6933618Abstract: A tablet for producing a semiconductor device with substantially no bowing, comprising an epoxy resin composition comprising an epoxy resin and a curing agent, wherein the tablet has the characteristic of an amount reduced by heating being less than 0.05% by weight; a wafer with a resin layer and a semiconductor device produced by using the tablet; and a process for producing the wafer and the semiconductor device.Type: GrantFiled: May 12, 2004Date of Patent: August 23, 2005Assignee: Nitto Denko CorporationInventors: Akihisa Kuroyanagi, Hisataka Ito, Shinichirou Sudo, Hirofumi Oono
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Patent number: 6852263Abstract: A tablet for producing a semiconductor device with substantially no bowing, comprising an epoxy resin composition comprising an epoxy resin and a curing agent, wherein the tablet has the characteristic of an amount reduced by heating being less than 0.05% by weight; a wafer with a resin layer and a semiconductor device produced by using the tablet; and a process for producing the wafer and the semiconductor device.Type: GrantFiled: September 16, 2003Date of Patent: February 8, 2005Assignee: Nitto Denko CorporationInventors: Akihisa Kuroyanagi, Hisataka Ito, Shinichirou Sudo, Hirofumi Oono
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Publication number: 20040210008Abstract: A tablet for producing a semiconductor device with substantially no bowing, comprising an epoxy resin composition comprising an epoxy resin and a curing agent, wherein the tablet has the characteristic of an amount reduced by heating being less than 0.05% by weight; a wafer with a resin layer and a semiconductor device produced by using the tablet; and a process for producing the wafer and the semiconductor device.Type: ApplicationFiled: May 12, 2004Publication date: October 21, 2004Applicant: Nitto Denko CorporationInventors: Akihisa Kuroyanagi, Hisataka Ito, Shinichirou Sudo, Hirofumi Oono
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Publication number: 20040052933Abstract: A tablet for producing a semiconductor device with substantially no bowing, comprising an epoxy resin composition comprising an epoxy resin and a curing agent, wherein the tablet has the characteristic of an amount reduced by heating being less than 0.05% by weight; a wafer with a resin layer and a semiconductor device produced by using the tablet; and a process for producing the wafer and the semiconductor device.Type: ApplicationFiled: September 16, 2003Publication date: March 18, 2004Applicant: NITTO DENKO CORPORATIONInventors: Akihisa Kuroyanagi, Hisataka Ito, Shinichirou Sudo, Hirofumi Oono
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Patent number: 6646063Abstract: A tablet for producing a semiconductor device with substantially no bowing, comprising an epoxy resin composition comprising an epoxy resin and a curing agent, wherein the tablet has the characteristic of an amount reduced by heating being less than 0.05% by weight; a wafer with a resin layer and a semiconductor device produced by using the tablet; and a process for producing the wafer and the semiconductor device.Type: GrantFiled: March 29, 2001Date of Patent: November 11, 2003Assignee: Nitto Denko CorporationInventors: Akihisa Kuroyanagi, Hisataka Ito, Shinichirou Sudo, Hirofumi Oono
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Publication number: 20010045671Abstract: A tablet for producing a semiconductor device with substantially no bowing, comprising an epoxy resin composition comprising an epoxy resin and a curing agent, wherein the tablet has the characteristic of an amount reduced by heating being less than 0.05% by weight; a wafer with a resin layer and a semiconductor device produced by using the tablet; and a process for producing the wafer and the semiconductor device.Type: ApplicationFiled: March 29, 2001Publication date: November 29, 2001Inventors: Akihisa Kuroyanagi, Hisataka Ito, Shinichirou Sudo, Hirofumi Oono