Abstract: For dividing a dividend of a first plurality of m-ary digits by a divisor of a second plurality of m-ary digits to provide a certain number K of m-ary quotient digits, where m represents 2.sup.N, a shift register comprises a most significant part, first and second higher parts for the second plurality less one of m-ary digits and one m-ary digit, and a least significant stage and holds an instantaneous content which is used as a current content during a last part of a preceding one of two consecutive machine cycles and is first a concatenation of an m-ary zero digit and the dividend m-ary digits. A carry save adder tree calculates a set of zeroth to (m-1)-th algebraic sums of a part of the current content held in the most significant and the first and the second higher parts minus zero through (m-1) times the divisor, respectively, plus a carry from a previous machine cycle. The sums are used in deciding a partial quotient of one m-ary digit and a sum datum of the second plurality of m-ary digits.

Abstract: In an error recovery system for use in combination with a multiprocessor system processing instructions under microprogram control which is energized on occurrence of an intermittent error in one of the processors to restart the microprogram from a checkpoint in the faulty processor when the microstep restart is allowable and which is energized upon occurrence of a physical error to make another processor take over execution of an instruction processed in the faulty processor, the faulty processor generates a physical error signal after completion of the microprogram restart so that another processor is forced to take over next succeeding procession to be carried out in the faulty processor. When retry of execution of the instruction is allowable on occurrence of the intermittent error, another processor is also forced to take over execution of the instruction.

Abstract: An early failure detection system for a multiprocessor system has a plurality of central processing units. When an idling central processing unit is detected by a microprogram stored in a control memory or a control memory controller, a test program for testing the idling central processing unit is executed before the idling central processing unit becomes busy. The test program is read out from a main memory and is executed using a register, an arithmetic circuit, an instruction advance fetching and decoding circuit, a main memory access control circuit, and the like. If a hardware failure of the idling central processing unit occurs during execution of the test program, the failed central processing unit is separated from the system so that the system can continue operation.