Abstract: The invention provides a bias circuit for suppressing change with temperature of an idle current of a power transistor and a semiconductor device including the bias circuit. The bias circuit includes a first bipolar transistor having an emitter, a base and a collector, and at least one Schottky diode connected to the base of the first bipolar transistor, and the at least one Schottky diode is provided for supplying a base potential for suppressing a collector current of the first bipolar transistor from changing in accordance with temperature change.

Abstract: The invention provides a bias circuit for suppressing change with temperature of an idle current of a power transistor and a semiconductor device including the bias circuit. The bias circuit includes a first bipolar transistor having an emitter, a base and a collector, and at least one Schottky diode connected to the base of the first bipolar transistor, and the at least one Schottky diode is provided for supplying a base potential for suppressing a collector current of the first bipolar transistor from changing in accordance with temperature change.

Abstract: The invention provides a bias circuit for suppressing change with temperature of an idle current of a power transistor and a semiconductor device including the bias circuit. The bias circuit includes a first bipolar transistor having an emitter, a base and a collector, and at least one Schottky diode connected to the base of the first bipolar transistor, and the at least one Schottky diode is provided for supplying a base potential for suppressing a collector current of the first bipolar transistor from changing in accordance with temperature change.

Abstract: A transistor includes a source region; a drain region; a channel region interposed between the source region and the drain region; and at least a first gate electrode and a second gate electrode provided on the channel region. At least one of the first and second gate electrodes traverses substantially an entire width of the channel region. At least another one of the first and second gate electrodes traverses a part of the width of the channel region.

Abstract: A transistor includes a source region; a drain region; a channel region interposed between the source region and the drain region; and at least a first gate electrode and a second gate electrode provided on the channel region. At least one of the first and second gate electrodes traverses substantially an entire width of the channel region. At least another one of the first and second gate electrodes traverses a part of the width of the channel region.

Abstract: A transistor includes: a source region; at least two drain regions; channels respectively disposed between the source region and each of the at least two drain regions; and a gate electrode provided on each of the channels. The at least two drain regions are electrically isolated from one another; and a drain electrode is provided on each of the drain regions.

Abstract: A plurality of ceramic substrates are stacked in layers to form a multilayer structure. A semiconductor chip having an FET or the like is mounted on the uppermost first ceramic substrate to form an RF matching circuit. A ground layer is formed on the second ceramic substrate, i.e., in a middle layer, thereby preventing the interference of electric signals between circuit components mounted in the respective layers upper and lower than the ground layer. A bias circuit is formed on the top face of the third ceramic substrate, while a back-face ground electrode is formed on the back face of the third ceramic substrate. A leadless electrode is formed over the side faces of the respective ceramic substrates and the back face of the lowermost third ceramic substrate. By utilizing the high heat conductivity and proper dielectric constant of aluminum nitride, the overall RF power amplifying circuit device can be miniaturized at lower cost.

Abstract: In a dual-mode radio telephone transmitter operative in both an analog modulation mode based on the FDMA system and a digital modulation mode based on the TDMA system, a DC bias voltage Vdd to be applied to a power amplification circuit is varied in accordance with the type of modulation, so that the input/output characteristics of the power amplification circuit can be optimized. To this end, a micro processor controls a switch interposed between the power amplification circuit and a positive DC power unit in such a manner that the DC bias voltage Vdd is 4.8 V for the FDMA mode, while the DC bias voltage Vdd is 6.0 V for the TDMA mode. The value of another DC bias voltage Vgg in the power amplification circuit is fixed. The value of the DC bias voltage Vdd is set higher in the TDMA mode than in the FDMA mode; thus, it becomes possible to increase the power added efficiency in the FDMA mode, without adversely affecting high linearity and high efficiency in the TDMA mode.