Abstract: An integrated circuit layout method comprising the steps of: laying out a plurality of circuit elements and a plurality of connecting wires connecting the circuit elements, on a chip; generating dummy patterns in regions that lie at an interval of a first distance from the connecting wires; and changing the first distance to a second distance that differs from the first distance, with respect to a part of connecting wires among said plurality of connecting wires. After layout, when a timing inspection is carried out by finding the delay values of the connecting wires through consideration of the dummy patterns, it is possible, with respect to a connecting wire of a path exhibiting a timing error, to adjust the separation distance to the dummy patterns (the width of the dummy pattern prohibition region) to thereby correct the delay value of this wiring path.

Abstract: An integrated circuit layout method comprising the steps of: laying out a plurality of circuit elements and a plurality of connecting wires connecting the circuit elements, on a chip; generating dummy patterns in regions that lie at an interval of a first distance from the connecting wires; and changing the first distance to a second distance that differs from the first distance, with respect to a part of connecting wires among said plurality of connecting wires. After layout, when a timing inspection is carried out by finding the delay values of the connecting wires through consideration of the dummy patterns, it is possible, with respect to a connecting wire of a path exhibiting a timing error, to adjust the separation distance to the dummy patterns (the width of the dummy pattern prohibition region) to thereby correct the delay value of this wiring path.