Patents by Inventor Akihito Anzai

Akihito Anzai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9628021
    Abstract: A wiring pattern for oscillation input signal and a wiring pattern for oscillation output signal are provided on a printed circuit board, and a wiring pattern for ground power source voltage is arranged in a region therebetween. A quartz crystal unit is connected between the wiring pattern for oscillation input signal and the wiring pattern for oscillation output signal and one ends of capacitors serving as load capacitors thereof are connected to the wiring pattern for ground power source voltage. Further, a wiring pattern for VSS is arranged so as to enclose these wiring patterns, and a wiring pattern for VSS is arranged also in a lower layer in addition thereto. By this means, reduction of a parasitic capacitance between an XIN node and an XOUT node, improvement in noise tolerance of these nodes and others can be achieved.
    Type: Grant
    Filed: February 15, 2016
    Date of Patent: April 18, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Osamu Ozawa, Masashi Horiguchi, Yuichi Okuda, Akihito Anzai
  • Publication number: 20160164461
    Abstract: A wiring pattern for oscillation input signal and a wiring pattern for oscillation output signal are provided on a printed circuit board, and a wiring pattern for ground power source voltage is arranged in a region therebetween. A quartz crystal unit is connected between the wiring pattern for oscillation input signal and the wiring pattern for oscillation output signal and one ends of capacitors serving as load capacitors thereof are connected to the wiring pattern for ground power source voltage. Further, a wiring pattern for VSS is arranged so as to enclose these wiring patterns, and a wiring pattern for VSS is arranged also in a lower layer in addition thereto. By this means, reduction of a parasitic capacitance between an XIN node and an XOUT node, improvement in noise tolerance of these nodes and others can be achieved.
    Type: Application
    Filed: February 15, 2016
    Publication date: June 9, 2016
    Inventors: Osamu Ozawa, Masashi Horiguchi, Yuichi Okuda, Akihito Anzai
  • Patent number: 9300248
    Abstract: A wiring pattern for oscillation input signal and a wiring pattern for oscillation output signal are provided on a printed circuit board, and a wiring pattern for ground power source voltage is arranged in a region therebetween. A quartz crystal unit is connected between the wiring pattern for oscillation input signal and the wiring pattern for oscillation output signal and one ends of capacitors serving as load capacitors thereof are connected to the wiring pattern for ground power source voltage. Further, a wiring pattern for VSS is arranged so as to enclose these wiring patterns, and a wiring pattern for VSS is arranged also in a lower layer in addition thereto. By this means, reduction of a parasitic capacitance between an XIN node and an XOUT node, improvement in noise tolerance of these nodes and others can be achieved.
    Type: Grant
    Filed: April 28, 2014
    Date of Patent: March 29, 2016
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Osamu Ozawa, Masashi Horiguchi, Yuichi Okuda, Akihito Anzai
  • Publication number: 20140232476
    Abstract: A wiring pattern for oscillation input signal and a wiring pattern for oscillation output signal are provided on a printed circuit board, and a wiring pattern for ground power source voltage is arranged in a region therebetween. A quartz crystal unit is connected between the wiring pattern for oscillation input signal and the wiring pattern for oscillation output signal and one ends of capacitors serving as load capacitors thereof are connected to the wiring pattern for ground power source voltage. Further, a wiring pattern for VSS is arranged so as to enclose these wiring patterns, and a wiring pattern for VSS is arranged also in a lower layer in addition thereto. By this means, reduction of a parasitic capacitance between an XIN node and an XOUT node, improvement in noise tolerance of these nodes and others can be achieved.
    Type: Application
    Filed: April 28, 2014
    Publication date: August 21, 2014
    Applicant: Renesas Electronics Corporation
    Inventors: Osamu Ozawa, Masashi Horiguchi, Yuichi Okuda, Akihito Anzai
  • Patent number: 8736390
    Abstract: A wiring pattern for oscillation input signal and a wiring pattern for oscillation output signal are provided on a printed circuit board, and a wiring pattern for ground power source voltage is arranged in a region therebetween. A quartz crystal unit is connected between the wiring pattern for oscillation input signal and the wiring pattern for oscillation output signal and one ends of capacitors serving as load capacitors thereof are connected to the wiring pattern for ground power source voltage. Further, a wiring pattern for VSS is arranged so as to enclose these wiring patterns, and a wiring pattern for VSS is arranged also in a lower layer in addition thereto. By this means, reduction of a parasitic capacitance between an XIN node and an XOUT node, improvement in noise tolerance of these nodes and others can be achieved.
    Type: Grant
    Filed: December 10, 2011
    Date of Patent: May 27, 2014
    Assignee: Rensas Electronics Corporation
    Inventors: Osamu Ozawa, Masashi Horiguchi, Yuichi Okuda, Akihito Anzai
  • Publication number: 20120161889
    Abstract: A wiring pattern for oscillation input signal and a wiring pattern for oscillation output signal are provided on a printed circuit board, and a wiring pattern for ground power source voltage is arranged in a region therebetween. A quartz crystal unit is connected between the wiring pattern for oscillation input signal and the wiring pattern for oscillation output signal and one ends of capacitors serving as load capacitors thereof are connected to the wiring pattern for ground power source voltage. Further, a wiring pattern for VSS is arranged so as to enclose these wiring patterns, and a wiring pattern for VSS is arranged also in a lower layer in addition thereto. By this means, reduction of a parasitic capacitance between an XIN node and an XOUT node, improvement in noise tolerance of these nodes and others can be achieved.
    Type: Application
    Filed: December 10, 2011
    Publication date: June 28, 2012
    Inventors: Osamu OZAWA, Masashi Horiguchi, Yuichi Okuda, Akihito Anzai