Abstract: A semiconductor storage device includes: a substrate layer; and a stacked body that is provided on the substrate layer. The semiconductor storage device includes a columnar portion that includes a semiconductor body extending within the stacked body in a stacking direction. The semiconductor storage device includes: an insulating layer provided on the plurality of terrace portions; and a plurality of columnar bodies extending in a first direction and provided within the insulating layer. The semiconductor storage device includes slit portions that split the stacked body into a plurality of string units. Each of the columnar bodies adjacent to each of the slit portions has a core film, the semiconductor body, a tunnel insulating film, and a block insulating film formed in sequence from a shaft center side to an outer periphery side of the columnar body, and the columnar body does not have the charge storage portion.

Abstract: A semiconductor storage device includes: a substrate layer; and a stacked body that is provided on the substrate layer and that includes a plurality of electrode layers stacked in a first direction via insulators, the stacked body including staircase portions in which the plurality of electrode layers include a plurality of terrace portions. The semiconductor storage device includes a columnar portion that includes a semiconductor body extending within the stacked body in a stacking direction of the stacked body, i.e., the first direction and a charge storage portion provided between the semiconductor body and the electrode layers. The semiconductor storage device includes: an insulating layer provided on the plurality of terrace portions; and a plurality of columnar bodies extending in the first direction and provided within the insulating layer. The semiconductor storage device includes slit portions that split the stacked body into a plurality of string units.

Abstract: A memory device includes a substrate, a first conductive layer above the substrate and extending in a first direction parallel to a surface of the substrate, a second conductive layer above the first conductive layer and extending in the first direction, wherein centers of the first and second conductive layers are aligned in a second direction that is substantially perpendicular to the surface of the substrate, and a contact extending in the second direction from a position lower than the first conductive layer to a position higher than the second conductive layer, the contact being electrically connected to and in direct contact with the first conductive layer and electrically insulated and physically separated from the second conductive layer.

Abstract: The embodiments provide a semiconductor memory device including: a plurality of first wiring lines extending in a first direction, the first wiring lines being provided in a second direction intersecting the first direction; a plurality of second wiring lines extending in the second direction, the second wiring lines being provided in the first direction; a plurality of memory cells provided in the intersections between the first wiring lines and the second wiring lines, each memory cell having a first stack structure comprising at least a variable resistor film; a contact extending in a third direction intersecting the first and second directions, the contact having a first end connected to one of the first wiring lines or one of the second wiring lines, the contact having a second stack structure having a stack of a plurality of films; and a wiring layer connected to a second end of the contact.

Abstract: The embodiments provide a semiconductor memory device including: a plurality of first wiring lines extending in a first direction, the first wiring lines being provided in a second direction intersecting the first direction; a plurality of second wiring lines extending in the second direction, the second wiring lines being provided in the first direction; a plurality of memory cells provided in the intersections between the first wiring lines and the second wiring lines, each memory cell having a first stack structure comprising at least a variable resistor film; a contact extending in a third direction intersecting the first and second directions, the contact having a first end connected to one of the first wiring lines or one of the second wiring lines, the contact having a second stack structure having a stack of a plurality of films; and a wiring layer connected to a second end of the contact.

Abstract: A memory device includes a substrate, a first conductive layer above the substrate and extending in a first direction parallel to a surface of the substrate, a second conductive layer above the first conductive layer and extending in the first direction, wherein centers of the first and second conductive layers are aligned in a second direction that is substantially perpendicular to the surface of the substrate, and a contact extending in the second direction from a position lower than the first conductive layer to a position higher than the second conductive layer, the contact being electrically connected to and in direct contact with the first conductive layer and electrically insulated and physically separated from the second conductive layer.

Abstract: A semiconductor device including a semiconductor substrate having an active region and an element isolation region; memory-cell transistors and select-gate transistors each formed above the substrate and having a gate electrode formed above the active region via a first insulating film, the gate electrode including a floating gate electrode, an interelectrode insulating film, and a control gate electrode; the element isolation region being formed of a trench and an insulating film filled in the trench, a position of an upper surface of the insulating film located between the gate electrodes of the memory cell transistors being higher than a position of the upper surface of the floating gate electrode, and a position of an upper surface of the insulating film located between the gate electrodes of the select-gate transistors being lower than a position of the upper surface of the floating gate electrode.