Patents by Inventor Akihito Ishimura

Akihito Ishimura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240196568
    Abstract: A semiconductor memory device includes a substrate, a plurality of memory chips, a controller, a plurality of terminals, a sealing member, and a sheet. The substrate has a first plane and a second plane positioned on an opposite side of the first plane. The plurality of memory chips are mounted on the first plane of the substrate. The controller is mounted on the first plane of the substrate to control the plurality of memory chips. The plurality of terminals provided on the second plane of the substrate and including a plurality of test terminals. The sealing member seals the first plane of the substrate, the plurality of memory chips, and the controller. The sheet covers the plurality of test terminals among the plurality of terminal. The sheet is an insulator and has a thermal conductivity of from 1.0 W/(m·K) to 8.0 W/(m·K).
    Type: Application
    Filed: February 22, 2024
    Publication date: June 13, 2024
    Applicant: KIOXIA CORPORATION
    Inventor: Akihito ISHIMURA
  • Patent number: 9136252
    Abstract: A semiconductor device includes a substrate having a first surface, a height adjuster mounted on the first surface of the substrate via a first adhesive layer, a semiconductor chip mounted on the height adjuster via a second adhesive layer, an electronic component mounted on the first surface of the substrate via a third adhesive layer, a bonding wire, and a sealing member. The length of the electronic component in a first direction corresponding to the thickness direction of the substrate is larger than the length of the semiconductor chip in the first direction, and the sum of the lengths of the height adjuster, the second adhesive layer, and the semiconductor chip in the first direction is larger than the length of the electronic component in the first direction.
    Type: Grant
    Filed: August 30, 2013
    Date of Patent: September 15, 2015
    Assignee: Kabushiki Kaishi Toshiba
    Inventors: Akihiro Iida, Akihito Ishimura, Hiroshi Inagaki
  • Publication number: 20140197550
    Abstract: A semiconductor device includes a substrate having a first surface, a height adjuster mounted on the first surface of the substrate via a first adhesive layer, a semiconductor chip mounted on the height adjuster via a second adhesive layer, an electronic component mounted on the first surface of the substrate via a third adhesive layer, a bonding wire, and a sealing member. The length of the electronic component in a first direction corresponding to the thickness direction of the substrate is larger than the length of the semiconductor chip in the first direction, and the sum of the lengths of the height adjuster, the second adhesive layer, and the semiconductor chip in the first direction is larger than the length of the electronic component in the first direction.
    Type: Application
    Filed: August 30, 2013
    Publication date: July 17, 2014
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Akihiro IIDA, Akihito ISHIMURA, Hiroshi INAGAKI
  • Patent number: 7339257
    Abstract: A lead frame has a plurality of first inner leads having distal end portions and parallel to each other, and a plurality of second inner leads having distal end portions opposing the distal end portions of the first inner leads, longer than the first inner leads, and parallel to each other. The semiconductor chip has a plurality of bonding pads arranged along one side of an element formation surface, and is mounted on the surfaces of the plurality of second inner leads using an insulating adhesive. The plurality of bonding wires include first bonding wires which electrically connect the distal end portions of the plurality of first inner leads to some of the plurality of bonding pads, and a plurality of second bonding wires which electrically connect the distal end portions of the plurality of second inner leads to the rest of the plurality of bonding pads.
    Type: Grant
    Filed: April 26, 2005
    Date of Patent: March 4, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Isao Ozawa, Akihito Ishimura, Yasuo Takemoto, Tetsuya Sato
  • Publication number: 20050236698
    Abstract: A lead frame has a plurality of first inner leads having distal end portions and parallel to each other, and a plurality of second inner leads having distal end portions opposing the distal end portions of the first inner leads, longer than the first inner leads, and parallel to each other. The semiconductor chip has a plurality of bonding pads arranged along one side of an element formation surface, and is mounted on the surfaces of the plurality of second inner leads using an insulating adhesive. The plurality of bonding wires include first bonding wires which electrically connect the distal end portions of the plurality of first inner leads to some of the plurality of bonding pads, and a plurality of second bonding wires which electrically connect the distal end portions of the plurality of second inner leads to the rest of the plurality of bonding pads.
    Type: Application
    Filed: April 26, 2005
    Publication date: October 27, 2005
    Inventors: Isao Ozawa, Akihito Ishimura, Yasuo Takemoto, Tetsuya Sato