Patents by Inventor Akihito Kobayashi

Akihito Kobayashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20080215810
    Abstract: A RAID control apparatus and control method. The RAID control apparatus includes disk devices and disk control devices including a cache memory that stores cache data of a logical unit, and control unit, upon the logical units present in different disk devices being concatenated to each other, switching in-charge disk control devices such that a disk control device is in charge of access to the concatenated logical units without writing back the cache data stored in a cache memory of a source disk control device to the disk device.
    Type: Application
    Filed: February 7, 2008
    Publication date: September 4, 2008
    Applicant: FUJITSU LIMITED
    Inventors: Hidenori YAMADA, Akihito Kobayashi, Katsuhiko Nagashima
  • Publication number: 20080203623
    Abstract: A resin fuel tank having a two-layer structure of inner and outer layers is formed by rotational molding so as to be superior not only in appearance but also in weathering resistance, low temperature impact resistance and resistance to gasoline permeability.
    Type: Application
    Filed: April 21, 2008
    Publication date: August 28, 2008
    Applicant: HONDA MOTOR CO., LTD.
    Inventors: Nobuo Fujitaka, Akihito Kobayashi
  • Patent number: 7320055
    Abstract: A cache processing unit manages the data, which is in a cache memory, in a page unit including plurality pieces of block data each of which serves as an access unit of a host, and processes input and output requests from a host to a storage device. In a case in which dirty data in a cache memory which is updated by a host and newer than stored data in a storage device is to be written back to the storage device, and when an incontinuous area is determined in a page of the dirty data, a write-back process unit reads out an incontinuous area from a storage device when a read command is issued, subjects it to a merge so as to generate a continuous area, and performs a write back by one time of write command issue.
    Type: Grant
    Filed: March 28, 2005
    Date of Patent: January 15, 2008
    Assignee: Fujitsu Limited
    Inventors: Mikio Ito, Akihito Kobayashi
  • Publication number: 20070294475
    Abstract: A cache managing unit creates a list of elements corresponding to each data block arranged based on a priority of writing data blocks to a magnetic disk apparatus, and when a group of elements corresponding to data blocks to be written to the same magnetic disk apparatus exists, provides a link connecting elements at both ends of the group. A write control unit searches, upon selecting a data block for writing, elements belonging to the list in descending order of priority, and if a link is set at an element corresponding to a data block to be written to a magnetic disk that cannot perform a writing, follows the link to search a subsequent element.
    Type: Application
    Filed: October 31, 2006
    Publication date: December 20, 2007
    Applicant: FUJITSU LIMITED
    Inventors: Akihito Kobayashi, Katsuhiko Nagashima, Hidenori Yamada
  • Publication number: 20070259121
    Abstract: A part provided with an oil-repellent coating having an oil repellency great enough to enable droplets of fuel and lubricating oil to quickly slide off from the surface in the vicinity of an injection port of a fuel injector and a method of production of the same are provided. A part comprised of a metal base material on the surface of which an oil-repellent coating is provided, said part provided with an oil-repellent coating wherein said oil-repellent coating is constituted by a bottom layer of PES (polyether sulfone) adhered to a surface of the base material and a top layer formed by dispersion of discrete phases of FEP (tetrafluoroethylene-hexafluoropropylene copolymer) in a continuous phase of PES integrally formed with the PES of the bottom layer and wherein the top layer is exposed as the surface of the oil-repellent coating. A weight ratio PES wt %:FEP wt % of PES and PEP which form the oil-repellent coating is preferably 40:60 to 80:20, more preferably 60:40 to 75:25.
    Type: Application
    Filed: May 19, 2006
    Publication date: November 8, 2007
    Inventors: Kazuhiko Shiratani, Syoji Miyazaki, Katsumi Sakamoto, Akihito Kobayashi
  • Publication number: 20070079064
    Abstract: In order to provide a disk cache control apparatus allowing an upper level apparatus to carry out a high speed access even if the upper level apparatus accesses a discretionary area of a logical volume, the disk cache control apparatus comprises at least a data storage unit for storing data read out of a lower level apparatus temporarily or for a predefined time, a management information storage unit for storing management information which correlates an area of a logical volume with that of the data storage unit, a management information generation unit for generating the management information, and an access processing unit for accessing data of either the data storage unit or a lower level apparatus.
    Type: Application
    Filed: December 29, 2005
    Publication date: April 5, 2007
    Applicant: Fujitsu Limited
    Inventors: Akihito Kobayashi, Hidenori Yamada, Katsuhiko Nagashima, Mikio Ito
  • Publication number: 20070005885
    Abstract: An interdevice communication monitoring unit 62-1 calculates a variable timeout time (T2?T) by subtracting an elapsed time T from a predetermined fixed timeout time T2 for monitoring an intermodule communication to monitor an elapsed time of an intermodule communication. The fixed timeout time T2 is a time shorter than a predetermined interface connection check time T1 for monitoring an interface connection with a channel. When the elapsed time T of the intermodule communication exceeds the variable timeout time (T2?T), the interdevice communication monitoring unit requests a channel to separate the interface connection, and then when an end response is obtained from a control module, requests the channel for an interface reconnection and then transmits an end response.
    Type: Application
    Filed: September 20, 2005
    Publication date: January 4, 2007
    Applicant: FUJITSU LIMITED
    Inventors: Akihito Kobayashi, Hidenori Yamada, Katsuhiko Nagashima, Hideaki Omura, Koji Uchida, Shinichi Nishizono
  • Patent number: 7159071
    Abstract: A storage system prevents a time out error of the host I/O caused by a stagnation of command processing in the storage system for accessing a disk device according to the host I/O request and internal I/O request. In DTC, counters for managing the requests in-process for host I/Os (host read) and internal I/Os (pre-fetch, write back) individually are provided, and the number of processing requests to be issued to a virtual disk (RLU) is limited individually. By assigning priority to the host I/Os, the load balance of the host I/Os and internal I/Os can be controlled. For rebuild/copy back, a dedicated load control mechanism is disposed where the load adjustment between ordinary I/Os and rebuild/copy back is performed.
    Type: Grant
    Filed: February 26, 2004
    Date of Patent: January 2, 2007
    Assignee: Fujitsu Limited
    Inventors: Kazuhiko Ikeuchi, Mikio Ito, Hidejirou Daikokuya, Kazuma Takatsu, Katsuhiko Nagashima, Koji Uchida, Akihito Kobayashi
  • Patent number: 7143209
    Abstract: A storage control apparatus concatenates a plurality of logical units to construct a large capacity logical unit, wherein logical units extending over a plurality of controllers can be concatenated. The channel adapter sends an I/O request to one controller which charges one logical unit constituting the concatenation logical unit, out of a plurality of controllers when an I/O request is sent from a host to the concatenation logical unit LU linking a plurality of logical units, executes I/O processing in the one controller, then sends the I/O request to another controller which charges another logical unit constituting the concatenation logical unit, and continues I/O processing in the another controller.
    Type: Grant
    Filed: January 29, 2004
    Date of Patent: November 28, 2006
    Assignee: Fujitsu Limited
    Inventors: Koji Uchida, Takaaki Saito, Mikio Ito, Kazuma Takatsu, Hidejirou Daikokuya, Akihito Kobayashi, Kazuhiko Ikeuchi, Sanae Kamakura, Shinichi Nishizono
  • Publication number: 20060179219
    Abstract: A system creates a configuration definition table to be used for accessing a physical disk according to a host I/O request, to decrease a memory size of the configuration definition table even if common firmware is used for models with different scales. For this, a model correspondence table to show the definition of each model is provided in a configuration setup processing module, the maximum values of this model are recorded in a memory based on this content, and a memory area for each item is secured. And the actual content of the configuration definition is developed on the secured memory. Therefore even for a diversity of models, the memory size of the configuration definition table can be decreased to a size matching the model, with common firmware regardless the model.
    Type: Application
    Filed: September 30, 2005
    Publication date: August 10, 2006
    Applicant: FUJITSU LIMITED
    Inventors: Hidejirou Daikokuya, Mikio Ito, Kazuhiko Ikeuchi, Shinya Mochizuki, Katsuhiko Nagashima, Akihito Kobayashi, Koji Uchida, Shinichi Nishizono
  • Publication number: 20060179215
    Abstract: In the present invention, for each set of blocks [#(0) to #(N?1)] storing update data, a history block [#(N)] storing an update state value, for example, a generation, time or check code, showing an update state is provided, constituting a set of management data as a check object. When writing update data on a disk, a new update state value is calculated for the same set of management data and stored in memory as update state confirmation value. The new update state value is also set as write data in the history block in the same set of management data, and the entire of the set of management data including update data and update state value are written onto a disk. The history block is read and disk write omissions are detected by comparing the update state value and the update state confirmation value stored in memory.
    Type: Application
    Filed: May 18, 2005
    Publication date: August 10, 2006
    Applicant: FUJITSU LIMITED
    Inventors: Shinya Mochizuki, Hideo Takahashi, Mikio Ito, Hidejiro Daikokuya, Kazuhiko Ikeuchi, Hideki Yamanaka, Katsuhiko Nagashima, Akihito Kobayashi, Koji Uchida, Shinichi Nishizono
  • Publication number: 20060179217
    Abstract: In the present invention, for each set of blocks [#(0) to #(N-1)] storing update data, a history block [#(N)] storing an update state value, for example, a generation, time or check code, showing an update state is provided, constituting a set of management data as a check object. When writing update data on a disk, a new update state value is calculated for the same set of management data and stored in memory as update state confirmation value. The new update state value is also set as write data in the history block in the same set of management data, and the entire of the set of management data including update data and update state value are written onto a disk. The history block is read and disk write omissions are detected by comparing the update state value and the update state confirmation value stored in memory.
    Type: Application
    Filed: February 7, 2006
    Publication date: August 10, 2006
    Applicant: FUJITSU LIMITED
    Inventors: Mikio Ito, Hideo Takahashi, Shinya Mochizuki, Hidejiro Daikokuya, Kazuhiko Ikeuchi, Hideki Yamanaka, Katsuhiko Nagashima, Akihito Kobayashi, Koji Uchida, Shinichi Nishizono
  • Publication number: 20060123200
    Abstract: A cache processing unit manages the data, which is in a cache memory, in a page unit including plurality pieces of block data each of which serves as an access unit of a host, and processes input and output requests from a host to a storage device. In a case in which dirty data in a cache memory which is updated by a host and newer than stored data in a storage device is to be written back to the storage device, and when an incontinuous area is determined in a page of the dirty data, a write-back process unit reads out an incontinuous area from a storage device when a read command is issued, subjects it to a merge so as to generate a continuous area, and performs a write back by one time of write command issue.
    Type: Application
    Filed: March 28, 2005
    Publication date: June 8, 2006
    Applicant: FUJITSU LIMITED
    Inventors: Mikio Ito, Akihito Kobayashi
  • Publication number: 20060101216
    Abstract: A primary disk and a secondary disk that duplicates the data in the primary disk are connected to a host computer via a disk-array control unit. The disk-array control unit includes a plurality of central management units. Each central management unit includes a cache memory for writing data accessed, and a command-process executing unit that executes a process based on a command received. Each central management unit executes a process including determining, when there is an error in data stored in the primary disk while data stored in the secondary disk is normal, that a recovery process is necessary, duplicating, after completing an input/output process with the host computer, data written in the cache memory into a cache memory of any other central management unit, and writing-back the data written in the cache memory into the primary disk and the secondary disk.
    Type: Application
    Filed: February 28, 2005
    Publication date: May 11, 2006
    Applicant: FUJITSU LIMITED
    Inventors: Akihito Kobayashi, Katsuhiko Nagashima, Koji Uchida, Fumiaki Kobayashi
  • Publication number: 20060075187
    Abstract: A disk array device having a plurality of hard disk units has a large-capacity memory mounted on a controller module which controls the whole device. The large-capacity memory has a system area managed by an OS and a cache area serving as a cache memory, and in addition, it has a table area which stores management/control information of the device and whose area size is changeable at an arbitrary instance. Therefore, it is possible to change the table area according to the state of the device in an active state without ON/OFF of a power source, so that an area not in use in the table area can be released for use as the cache memory. This makes it possible to appropriately varying the sizes of the table area and the cache area in an active state while the device is in operation, thereby realizing effective use of the large-capacity memory.
    Type: Application
    Filed: January 31, 2005
    Publication date: April 6, 2006
    Applicant: FUJITSU LIMITED
    Inventors: Kazuo Nakashima, Osamu Kimura, Koji Uchida, Akihito Kobayashi
  • Publication number: 20060070238
    Abstract: A bearing apparatus includes a rotating member, a fixed member opposing the rotating member and an ink-like resin material. Opposing surfaces of the rotating member and the fixed member form a bearing part and the ink-like resin material is applied to at least one of the opposing surfaces by transfer printing.
    Type: Application
    Filed: November 18, 2005
    Publication date: April 6, 2006
    Inventors: Masato Gomyo, Shingo Suginobu, Nobutaka Nagao, Koichi Shoda, Akihito Kobayashi
  • Publication number: 20060068139
    Abstract: A resin fuel tank having a two-layer structure of inner and outer layers is formed by rotational molding so as to be superior not only in appearance but also in weathering resistance, low temperature impact resistance and resistance to gasoline permeability.
    Type: Application
    Filed: September 20, 2005
    Publication date: March 30, 2006
    Applicant: HONDA MOTOR CO., LTD.
    Inventors: Nobuo Fujitaka, Akihito Kobayashi
  • Patent number: 7008109
    Abstract: A dynamic pressure bearing device includes a dynamic pressure face of a shaft member, a dynamic pressure face of a bearing member, lubricating fluid filled in a bearing space of a dynamic pressure bearing portion including a gap between the dynamic pressure faces, a dynamic pressure generation means for pressing so that the lubricating fluid generates a dynamic pressure that supports the shaft member in a non-contact manner with the bearing member and in a rotatable manner relatively to the bearing member, and a sliding surface layer having abrasion resistance provided to at least one of the dynamic pressure face of the shaft member and the dynamic pressure face of the bearing member.
    Type: Grant
    Filed: February 10, 2004
    Date of Patent: March 7, 2006
    Assignees: Nidec Sankyo Corporation, Toyo Drilube. Co., Ltd.
    Inventors: Masato Gomyo, Noboru Ashibe, Masayoshi Saichi, Shingo Suginobu, Junya Mizukami, Nobutaka Nagao, Koichi Shoda, Akihito Kobayashi
  • Publication number: 20050216660
    Abstract: A RAID apparatus that at least duplicates identical data to store thus duplicated data, which, when an instruction of writing data is given, writes data to a local cache and to a mirror cache, and writes data of the local cache to a primary disk and writes data of the mirror cache to a secondary disk. When an instruction of reading out data is given, and specified data is retained in the caches, the RAID apparatus outputs valid data of the local cache or the mirror cache, while when specified data is not retained in the caches, the RAID apparatus outputs valid data of the primary disk or the secondary disk.
    Type: Application
    Filed: May 27, 2005
    Publication date: September 29, 2005
    Applicant: FUJITSU LIMITED
    Inventors: Akihito Kobayashi, Mikio Ito, Kazuma Takatsu, Koji Uchida, Hidejiro Daikokuya, Kazuhiko Ikeuchi
  • Publication number: 20050044300
    Abstract: The present invention has been developed to carry out the dual-writing of data in cache memories at a higher speed through a single address designation for the improvement of processing performance. In the present invention, a host interface module produces addressing information for designating two written-in destinations, and a bridge module produces two transferred-to addresses and written-in addresses of the cache memories on the basis of the addressing information so that data to be written is transferred to two management modules corresponding to the two transferred-to addresses to be written at the written-in addresses of the cache memories of the management modules.
    Type: Application
    Filed: February 25, 2004
    Publication date: February 24, 2005
    Applicant: Fujitsu Limited
    Inventors: Osamu Kimura, Yuichi Ogawa, Terumasa Haneda, Akihito Kobayashi, Koji Uchida, Kazuma Takatsu, Katsuhiko Nagashima