Patents by Inventor Akihito Miyamoto
Akihito Miyamoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240138695Abstract: A skin resistance measurement device includes a pair of electrode portions provided on an epidermis and a measurement portion configured to measure skin resistance between the pair of electrode portions. The pair of electrode portions has a structure in which drying of the epidermis is naturally performed.Type: ApplicationFiled: March 11, 2022Publication date: May 2, 2024Inventors: Takao SOMEYA, Akihito MIYAMOTO, Ikue KAWASHIMA, Masayuki AMAGAI, Hiroshi KAWASAKI
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Publication number: 20220240826Abstract: [Problem] Provided is an electronic functional member of superior wear resistance. [Solution] The present invention comprises a fiber network constituted by a water-soluble resin and a poorly water-soluble resin, and an electroconductive member formed on the fiber network. The water-soluble resin and poorly water-soluble resin are, for example, polyvinyl alcohol derivatives. In accordance with an embodiment of the electronic functional member according to the present invention, the fiber network is formed by layering a first fiber network constituted by fibers containing a water-soluble first resin and a second fiber network constituted by fibers containing a poorly water-soluble second resin. Alternatively, the fiber network may be constituted by fibers containing the water-soluble first resin and fibers containing the poorly water-soluble second resin. Alternatively, the fiber network may be constituted by fibers containing the water-soluble first resin and the poorly water-soluble second resin.Type: ApplicationFiled: March 6, 2020Publication date: August 4, 2022Inventors: Takao Someya, Akihito Miyamoto, Yan Wang, Sunghoon Lee, Shiho Nagai, Ikue Kawashima
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Publication number: 20220199286Abstract: [Problem] To provide an electronic functional member having high stretch-resistance. [Solution] An electronic functional member provided with: fibers formed in web-like shape and configuring a fiber web; a coating film coating the fibers and having a Young's modulus smaller than that of the fibers; and an electrically conductive film formed on the surface of the coating film.Type: ApplicationFiled: April 3, 2020Publication date: June 23, 2022Inventors: Takao Someya, Akihito Miyamoto, Yan Wang, Yorishige Matsuba, Ikue Kawashima
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Patent number: 10615243Abstract: The light-emitting device includes a flexible substrate, a lower barrier layer positioned above the flexible substrate, a light-emitting element and a thin-film transistor controlling the light-emitting element positioned above the lower barrier layer, a first upper barrier layer positioned above the light-emitting element and including a first inorganic material, and a second upper barrier layer positioned above the thin-film transistor and including a second inorganic material. The first upper barrier layer and the second upper barrier layer are spaced from each other at least in a region between the light-emitting element and the thin-film transistor.Type: GrantFiled: April 30, 2018Date of Patent: April 7, 2020Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Hiroaki Iijima, Akihito Miyamoto, Kenichi Sasai, Yoshichika Osada, Masumi Izuchi
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Publication number: 20200091271Abstract: The light-emitting device includes a flexible substrate, a lower barrier layer positioned above the flexible substrate, a light-emitting element and a thin-film transistor controlling the light-emitting element positioned above the lower barrier layer, a first upper barrier layer positioned above the light-emitting element and including a first inorganic material, and a second upper barrier layer positioned above the thin-film transistor and including a second inorganic material. The first upper barrier layer and the second upper barrier layer are spaced from each other at least in a region between the light-emitting element and the thin-film transistor.Type: ApplicationFiled: November 18, 2019Publication date: March 19, 2020Applicant: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Hiroaki IIJIMA, Akihito MIYAMOTO, Kenichi SASAI, Yoshichika OSADA, Masumi IZUCHI
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Publication number: 20180254312Abstract: The light-emitting device includes a flexible substrate, a lower barrier layer positioned above the flexible substrate, a light-emitting element and a thin-film transistor controlling the light-emitting element positioned above the lower barrier layer, a first upper barrier layer positioned above the light-emitting element and including a first inorganic material, and a second upper barrier layer positioned above the thin-film transistor and including a second inorganic material. The first upper barrier layer and the second upper barrier layer are spaced from each other at least in a region between the light-emitting element and the thin-film transistor.Type: ApplicationFiled: April 30, 2018Publication date: September 6, 2018Applicant: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LT D.Inventors: Hiroaki IIJIMA, Akihito MIYAMOTO, Kenichi SASAI, Yoshichika OSADA, Masumi IZUCHI
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Patent number: 9991326Abstract: The light-emitting device according to one aspect of the present disclosure includes a flexible substrate, a lower barrier layer positioned above the flexible substrate, a first light-emitting element and a second light-emitting element positioned above the lower barrier layer, a first upper barrier layer positioned above the first light-emitting element and including a first inorganic material, and a second upper barrier layer positioned above the second light-emitting element and including a second inorganic material. The first upper barrier layer and the second upper barrier layer are spaced from each other at least in a region between the first light-emitting element and the second light-emitting element.Type: GrantFiled: January 6, 2016Date of Patent: June 5, 2018Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Hiroaki Iijima, Akihito Miyamoto, Kenichi Sasai, Yoshichika Osada, Masumi Izuchi
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Patent number: 9837692Abstract: A power controlling apparatus includes a secondary battery (2) connected to an electrical device (4), and a fuel cell (3) connected to the electrical device (4) and the secondary battery (2). The fuel cell (3) has two non-generating modes including an idling mode and a halt mode, the fuel cell (3) suspending generation of power while being supplied with fuel in the idling mode, the fuel cell (3) stopping generation of power without fuel supply in the halt mode. The power controlling apparatus further includes a remainder estimator (11) to calculate the remaining number of starts representing the remaining number of available starts of the fuel cell (3), and a controller (16) to control the fuel cell (3) to be one of the two non-generating modes during a non-charging mode of the secondary battery (2), based on the remaining number of starts calculated by the remainder estimator (11).Type: GrantFiled: March 14, 2013Date of Patent: December 5, 2017Assignee: MITSUBISHI JIDOSHA KOGYO KABUSHIKI KAISHAInventors: Kazuhito Kawashima, Keisuke Tashiro, Tetsuya Watanabe, Akihito Miyamoto, Ryoji Kato, Chikara Takei
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Patent number: 9620731Abstract: A thin film transistor according to the present disclosure including: a gate electrode above a substrate; a gate insulating layer covering the gate electrode; a semiconductor layer above the gate insulating layer; and a source electrode and a drain electrode which are above the gate insulating layer, and electrically connected to the semiconductor layer, in which the gate insulating layer includes a first area and a second area, the first area being above the gate electrode, the second area being different from an area above the gate electrode, and made of a same substance as the first area, and the first area has a higher density than a density of the second area.Type: GrantFiled: September 24, 2013Date of Patent: April 11, 2017Assignee: PANASONIC COPRORATIONInventors: Takaaki Ukeda, Akihito Miyamoto, Norishige Nanai
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Publication number: 20160204185Abstract: The light-emitting device according to one aspect of the present disclosure includes a flexible substrate, a lower barrier layer positioned above the flexible substrate, a first light-emitting element and a second light-emitting element positioned above the lower barrier layer, a first upper barrier layer positioned above the first light-emitting element and including a first inorganic material, and a second upper barrier layer positioned above the second light-emitting element and including a second inorganic material. The first upper barrier layer and the second upper barrier layer are spaced from each other at least in a region between the first light-emitting element and the second light-emitting element.Type: ApplicationFiled: January 6, 2016Publication date: July 14, 2016Inventors: HIROAKI IIJIMA, AKIHITO MIYAMOTO, KENICHI SASAI, YOSHICHIKA OSADA, MASUMI IZUCHI
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Patent number: 9312283Abstract: In a method for producing a display panel, a base substrate having an upper surface on which an electrode is located is prepared. A first layer having a first opening overlapping with the electrode in plan-view is formed on the base substrate. A second layer having a second opening overlapping with the first opening in plan-view is formed on the first layer. The second opening has a smaller area than the first opening in plan-view. A wiring layer is formed in the first opening and the second opening, in contact with the electrode. The second layer includes a portion located on an upper surface of the first layer and a portion located in the first opening. The portion of the second layer located in the first opening covers an internal side surface of the first layer located around the first opening.Type: GrantFiled: March 18, 2014Date of Patent: April 12, 2016Assignee: JOLED INC.Inventors: Norishige Nanai, Takaaki Ukeda, Akihito Miyamoto
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Patent number: 9190430Abstract: A method of manufacturing a display panel includes a sub-step of forming a photosensitive material layer for formation of a second layer on a first layer, a sub-step of disposing, over the photosensitive material layer, a photomask having a different degree of transparency in a first region and a second region thereof, the first region overlapping the photosensitive material layer, in plan view, at a location for formation of a second aperture, and the second region being a remainder of the photomask other than the first region, and a sub-step of exposing the photosensitive material layer via the photomask. In plan view, the area of the first region in the photomask is larger than the area of a first aperture in the first layer.Type: GrantFiled: January 10, 2013Date of Patent: November 17, 2015Assignee: JOLED INC.Inventors: Norishige Nanai, Akihito Miyamoto, Takaaki Ukeda
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Publication number: 20150295293Abstract: A power controlling apparatus includes a secondary battery (2) connected to an electrical device (4), and a fuel cell (3) connected to the electrical device (4) and the secondary battery (2). The fuel cell (3) has two non-generating modes including an idling mode and a halt mode, the fuel cell (3) suspending generation of power while being supplied with fuel in the idling mode, the fuel cell (3) stopping generation of power without fuel supply in the halt mode. The power controlling apparatus further includes a remainder estimator (11) to calculate the remaining number of starts representing the remaining number of available starts of the fuel cell (3), and a controller (16) to control the fuel cell (3) to be one of the two non-generating modes during a non-charging mode of the secondary battery (2), based on the remaining number of starts calculated by the remainder estimator (11).Type: ApplicationFiled: March 14, 2013Publication date: October 15, 2015Applicant: MITSUBISHI JIDOSHA KOGYO KABUSHIKI KAISHAInventors: Kazuhito Kawashima, Keisuke Tashiro, Tetsuya Watanabe, Akihito Miyamoto, Ryoji Kato, Chikara Takei
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Patent number: 9117942Abstract: An electronic device including: a substrate; a bank formed above the substrate; a semiconductor layer formed within an aperture surrounded by the bank; and electrodes electrically connected to the semiconductor layer. An outline of the aperture in plan view includes a first straight edge, a second straight edge continuous with one end of the first edge via a first connector, and a straight third edge continuous with the other end of the first edge via a second connector. The area of a first connector region differs from the area of a second connector region, the first connector region being defined by a first imaginary straight line along the first edge, a second imaginary straight line along the second edge, and the first connector, and the second connector region being defined by a third imaginary straight line along the third edge, the first imaginary straight line, and the second connector.Type: GrantFiled: November 24, 2014Date of Patent: August 25, 2015Assignee: PANASONIC CORPORATIONInventors: Akihito Miyamoto, Yuko Okumoto
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Patent number: 9112162Abstract: An electronic device including: a substrate; a bank formed on an upper surface of the substrate, surrounding an area of the upper surface of the substrate, and defining an aperture from which the area is exposed; a liquid-philic layer formed on a peripheral portion of the area, and not overlapping a central portion of the area; a semiconductor layer formed within the aperture, and attaching to at least a portion of the central portion and to an upper surface of the liquid-philic layer; and a pair of electrodes that are in contact with an area of the semiconductor layer, the area of the semiconductor layer not overlapping the liquid-philic layer in plan view. The bank has a liquid-phobic lateral surface surrounding the aperture, and the upper surface of the liquid-philic layer has a higher degree of liquid-philicity than the upper surface of the substrate.Type: GrantFiled: November 24, 2014Date of Patent: August 18, 2015Assignee: PANASONIC CORPORATIONInventors: Akihito Miyamoto, Yuko Okumoto
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Patent number: 9024319Abstract: A thin film transistor element is formed in each of adjacent first and second apertures defined by partition walls. In plan view of a bottom portion of the first aperture, a center of a total of areas of a source electrode portion and a drain electrode portion is offset from a center of area of the bottom portion in a direction opposite a direction of the second aperture, and in plan view of a bottom portion of the second aperture, a center of a total of areas of a source electrode portion and a drain electrode portion is offset from a center of area of the bottom portion in a direction opposite a direction of the first aperture.Type: GrantFiled: August 16, 2013Date of Patent: May 5, 2015Assignee: Panasonic CorporationInventors: Yuko Okumoto, Akihito Miyamoto, Takaaki Ukeda
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Patent number: 9024449Abstract: A thin film transistor element includes: a gate electrode; a source electrode and a drain electrode; an insulating layer; partition walls; and an organic semiconductor layer. The partition walls define a first aperture. Within the first aperture, at least a part of the source electrode and at least a part of the drain electrode are in contact with the semiconductor layer. The partition walls have side face portions facing the first aperture, and some of the side face portions have gentler slopes than the rest of the side face portions.Type: GrantFiled: October 22, 2013Date of Patent: May 5, 2015Assignee: Panasonic CorporationInventors: Yuko Okumoto, Akihito Miyamoto, Takaaki Ukeda
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Patent number: 9018704Abstract: The organic thin-film transistor according to the present invention includes: a gate electrode line on a substrate in a first region: a first signal line layer in a second region; a gate insulating film covering the gate electrode line and the first signal line layer; bank layers on the gate insulating film; a second signal line layer on the bank layer over the first signal line; a drain electrode and a source electrode line which are located on the bank layers and in at least one opening between the bank layers in the first region; a semiconductor layer located at least in the opening and banked up by the bank layers, the drain electrode, and the source electrode line; and a protection film covering the semiconductor layer.Type: GrantFiled: October 20, 2011Date of Patent: April 28, 2015Assignee: Panasonic CorporationInventors: Takaaki Ukeda, Akihito Miyamoto
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Publication number: 20150102333Abstract: An electronic device including: a substrate; a bank formed above the substrate; a semiconductor layer formed within an aperture surrounded by the bank; and electrodes electrically connected to the semiconductor layer. An outline of the aperture in plan view includes a first straight edge, a second straight edge continuous with one end of the first edge via a first connector, and a straight third edge continuous with the other end of the first edge via a second connector. The area of a first connector region differs from the area of a second connector region, the first connector region being defined by a first imaginary straight line along the first edge, a second imaginary straight line along the second edge, and the first connector, and the second connector region being defined by a third imaginary straight line along the third edge, the first imaginary straight line, and the second connector.Type: ApplicationFiled: November 24, 2014Publication date: April 16, 2015Applicant: PANASONIC CORPORATIONInventors: Akihito MIYAMOTO, Yuko OKUMOTO
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Patent number: 8994186Abstract: A thin film transistor element includes: a gate electrode; a source electrode and a drain electrode; an insulating layer; partition walls; and an organic semiconductor layer. The partition walls define a first aperture. Within the first aperture, at least a part of the source electrode and at least a part of the drain electrode are in contact with the semiconductor layer. In plan view of the bottom of the first aperture, the center of the total of the areas of the source electrode and the drain electrode is offset from the center of the area of the bottom in a given direction.Type: GrantFiled: October 23, 2013Date of Patent: March 31, 2015Assignee: Panasonic CorporationInventors: Yuko Okumoto, Akihito Miyamoto, Takaaki Ukeda