Abstract: The CPU speed is apparently decreased, and current consumption is reduced by asserting a stop clock (STPCLK#) signal at a predetermined interval. When a system event (INTR, NMI, SMI, SRESET, and INIT) occurs, assertion of the STPCLK# signal is inhibited for a predetermined time to allow a high-speed operation. In an ISA refresh cycle, by asserting the STPCLK# signal instead of a conventional HOLD/HLDA cycle, the refresh cycle is executed in a stop grant state.

Abstract: In a controller which generates a clock to be output to a CPU on the basis of a fundamental clock, and incorporates control logic circuits such as DRAM control, CPU cycle control, and the like, the internal operation clock is switched to either an internally generated clock or a clock obtained by re-inputting a clock which is temporarily output to an external circuit. Only the clock to be output to the CPU can be delayed with respect to the clock used for generating a DRAM control signal, and the delay time of the DRAM control signal with respect to the CPU clock can be minimized.

Abstract: A system controller is provided with an ISA bus controller that executes a command cycle at a speed complying with the standards for ISA buses and a high-speed bus controller that executes a command cycle at a higher speed. When an I/O device that can operate at higher speeds than that of the ISA bus for a PCMCIA controller and IDE interface, a high-speed bus controller is used in place of the ISA bus controller. The high-speed bus controller executes a command cycle at a speed corresponding to the performance of the addressed I/O device. When a busy signal (an inactive IORDY signal) indicating that data transfer is not in time is outputted from the I/O device side, the cycle width of the command is lengthened. There are a synchronous sampling mode and an asynchronous sampling mode for the IORDY signal. The cycle from when IORDY goes off until the command goes off is set in a programmable manner.

Abstract: A personal computer system is provided with a detachable hard disk pack, a lock mechanism for locking the hard disk pack into the system, a switch which turns on and off in cooperation with the lock and release operations of the lock mechanism. When the hard disk pack is detached from the system, while the system is being powered, the switch turns off in cooperation with the release operation of the lock mechanism. In response to the changed state of the switch, the NMI control section outputs an NMI signal to the CPU. In response to the NMI signal, the CPU instructs a power controller to cut off the power. The CPU determines in response to the system being powered if the hard disk pack is attached to the system. If the hard disk pack is not attached, the CPU instructs the power controller not to supply the power to the system.