Patents by Inventor Akihito Narita
Akihito Narita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11951920Abstract: The present invention relates to an operation device which can be easily installed on a vehicle door, and a vehicle door comprising the operation device. An operation device of the present invention comprises: a gripper provided on an inner surface of a door of a vehicle; an operation interface provided on an inner side surface of the gripper for receiving an operation input entered by an occupant to operate at least one in-vehicle device; a first sensor provided on an outer side surface of the gripper for detecting a finger of the occupant; a second sensor provided on at least one of the inner side surface and an upper surface of the gripper for detecting a finger of the occupant; and a controller connected to the operation interface, the first sensor, the second sensor, and the at least one in-vehicle device.Type: GrantFiled: March 13, 2020Date of Patent: April 9, 2024Assignee: TS TECH CO., LTD.Inventors: Jinichi Tanabe, Takayoshi Ito, Kazumasa Narita, Yuma Miyamoto, Akihito Kobayashi, Kodai Matsumoto
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Patent number: 7986046Abstract: A semiconductor module including: a semiconductor chip in which an integrated circuit is formed; an electrode formed on the semiconductor chip and electrically connected to the integrated circuit; an insulating film formed on the semiconductor chip and having an opening positioned corresponding to the electrode; an elastic protrusion disposed on the insulating film, a surface of the elastic protrusion opposite to the insulating film being convexly curved; an interconnect extending from over the electrode to over the elastic protrusion; an elastic substrate on which a lead is formed, the lead being in contact with part of the interconnect positioned on the elastic protrusion; and an adhesive maintaining a space between a surface of the semiconductor chip on which the elastic protrusion is formed and a surface of the elastic substrate on which the lead is formed. The elastic substrate has a first depression formed by elastic deformation.Type: GrantFiled: February 25, 2009Date of Patent: July 26, 2011Assignee: Seiko Epson CorporationInventors: Akihito Narita, Naoya Sato
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Patent number: 7893543Abstract: A semiconductor module including: a semiconductor chip, an integrated circuit being formed in the semiconductor chip; a plurality of electrodes electrically connected to the integrated circuit; an insulating film formed on the semiconductor chip and having a plurality of openings positioned corresponding to the plurality of electrodes; and a long elastic protrusion extending on the insulating film. A plurality of interconnects respectively extend from over the electrodes to over the elastic protrusion, directions of the interconnects intersecting an axis AX that is parallel to the extending direction of the elastic protrusion. A plurality of leads are respectively in contact with the interconnects in an area positioned on the elastic protrusion. A cured adhesive maintains a space between a surface of the semiconductor chip on which the elastic protrusion is formed and a surface of the elastic substrate on which the leads are formed.Type: GrantFiled: February 25, 2009Date of Patent: February 22, 2011Assignee: Seiko Epson CorporationInventors: Akihito Narita, Naoya Sato
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Publication number: 20090218674Abstract: A semiconductor module including: a semiconductor chip, an integrated circuit being formed in the semiconductor chip; a plurality of electrodes electrically connected to the integrated circuit; an insulating film formed on the semiconductor chip and having a plurality of openings positioned corresponding to the plurality of electrodes; and a long elastic protrusion extending on the insulating film. A plurality of interconnects respectively extend from over the electrodes to over the elastic protrusion, directions of the interconnects intersecting an axis AX that is parallel to the extending direction of the elastic protrusion. A plurality of leads are respectively in contact with the interconnects in an area positioned on the elastic protrusion. A cured adhesive maintains a space between a surface of the semiconductor chip on which the elastic protrusion is formed and a surface of the elastic substrate on which the leads are formed.Type: ApplicationFiled: February 25, 2009Publication date: September 3, 2009Applicant: Seiko Epson CorporationInventors: Akihito NARITA, Naoya SATO
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Publication number: 20090218685Abstract: A semiconductor module including: a semiconductor chip in which an integrated circuit is formed; an electrode formed on the semiconductor chip and electrically connected to the integrated circuit; an insulating film formed on the semiconductor chip and having an opening positioned corresponding to the electrode; an elastic protrusion disposed on the insulating film, a surface of the elastic protrusion opposite to the insulating film being convexly curved; an interconnect extending from over the electrode to over the elastic protrusion; an elastic substrate on which a lead is formed, the lead being in contact with part of the interconnect positioned on the elastic protrusion; and an adhesive maintaining a space between a surface of the semiconductor chip on which the elastic protrusion is formed and a surface of the elastic substrate on which the lead is formed. The elastic substrate has a first depression formed by elastic deformation.Type: ApplicationFiled: February 25, 2009Publication date: September 3, 2009Applicant: SEIKO EPSON CORPORATIONInventors: Akihito NARITA, Naoya SATO
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Patent number: 7257892Abstract: A method of manufacturing a wiring board, including: providing a resin substrate on which is formed a metal layer including a first layer and a second layer formed on the first layer; forming an interconnecting pattern by etching the metal layer so that the interconnecting pattern includes the patterned first layer and second layer and a part of the first layer remains outside the second layer as a residue of the first layer; electroless plating the interconnecting pattern and the residue of the first layer; and then washing the resin substrate. The washing of the resin substrate is performed by using at least one of an acidic solution used for dissolving and removing the residue of the first layer and a metal deposited on the residue of the first layer by the electroless plating and an alkaline solution used for dissolving the resin substrate to remove an area which supports the residue of the first layer.Type: GrantFiled: February 17, 2006Date of Patent: August 21, 2007Assignee: Seiko Epson CorporationInventors: Naoya Sato, Akihito Narita, Satoru Akatsuka, Tsutomu Abe
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Publication number: 20060185163Abstract: A method of manufacturing a wiring board, including: providing a resin substrate on which is formed a metal layer including a first layer and a second layer formed on the first layer; forming an interconnecting pattern by etching the metal layer so that the interconnecting pattern includes the patterned first layer and second layer and a part of the first layer remains outside the second layer as a residue of the first layer; electroless plating the interconnecting pattern and the residue of the first layer; and then washing the resin substrate. The washing of the resin substrate is performed by using at least one of an acidic solution used for dissolving and removing the residue of the first layer and a metal deposited on the residue of the first layer by the electroless plating and an alkaline solution used for dissolving the resin substrate to remove an area which supports the residue of the first layer.Type: ApplicationFiled: February 17, 2006Publication date: August 24, 2006Inventors: Naoya Sato, Akihito Narita, Satoru Akatsuka, Tsutomu Abe
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Publication number: 20060013947Abstract: A method for manufacturing a wiring board includes electroless plating wiring patterns provided on a base substrate and cleaning the base substrate. The step of cleaning the base substrate includes at least either using an alkaline solvent or using an acid solvent.Type: ApplicationFiled: July 8, 2005Publication date: January 19, 2006Inventors: Satoru Akatsuka, Tsutomu Abe, Toshinari Nanba, Naoya Sato, Akihito Narita