Patents by Inventor Akihito Sakakidani
Akihito Sakakidani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9577095Abstract: A semiconductor device includes a MISFET. The semiconductor device also includes a silicon nitride film 12 and a silicon nitride film 10 arranged on the silicon nitride film 12. The silicon nitride film 12 covers at least a portion of an upper part of a source/drain 8 of the MISFET and has a film thickness thinner than a height of a gate electrode 4. The source/drain 8 includes nickel silicide 9 on its boundary to the silicon nitride film 10. The silicon nitride film 10 is a stressed film. A tight adhering property between the silicon nitride film 12 and the surface of the source/drain 8 and that between the silicon nitride film 12 and the silicon nitride film 10 are rendered higher than a tight adhering property which would prevail when the silicon nitride film 10 be made to adhere tightly to the source/drain 8.Type: GrantFiled: April 30, 2015Date of Patent: February 21, 2017Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Kazuya Uejima, Hidetatsu Nakamura, Akihito Sakakidani, Eiichirou Watanabe
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Publication number: 20150236156Abstract: A semiconductor device includes a MISFET. The semiconductor device also includes a silicon nitride film 12 and a silicon nitride film 10 arranged on the silicon nitride film 12. The silicon nitride film 12 covers at least a portion of an upper part of a source/drain 8 of the MISFET and has a film thickness thinner than a height of a gate electrode 4. The source/drain 8 includes nickel silicide 9 on its boundary to the silicon nitride film 10. The silicon nitride film 10 is a stressed film. A tight adhering property between the silicon nitride film 12 and the surface of the source/drain 8 and that between the silicon nitride film 12 and the silicon nitride film 10 are rendered higher than a tight adhering property which would prevail when the silicon nitride film 10 be made to adhere tightly to the source/drain 8.Type: ApplicationFiled: April 30, 2015Publication date: August 20, 2015Inventors: Kazuya UEJIMA, Hidetatsu NAKAMURA, Akihito SAKAKIDANI, Eiichirou WATANABE
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Patent number: 8389350Abstract: A method of manufacturing N-type MOSFET includes: implanting a p-type dopant into in a surface layer of a semiconductor substrate to form a channel region; forming a gate insulating film including High-k material and a gate electrode on said channel region; implanting a p-type dopant into both ends of said channel region in an inner portion of said semiconductor substrate to form halo regions; implanting a p-type dopant into both ends of said channel region in a surface layer of said semiconductor substrate to form extension regions. One of said step of forming said channel region and said step of forming halo regions includes: implanting C into one of said channel region and said halo regions. An inclusion amount of said High-k material is an amount that increase of a threshold voltage caused by said High-k material being included in said gate insulating film compensates for decrease of said threshold voltage caused by said C being implanted.Type: GrantFiled: July 7, 2011Date of Patent: March 5, 2013Assignee: Renesas Electronics CorporationInventors: Akihito Sakakidani, Kiyotaka Imai
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Publication number: 20120181587Abstract: A semiconductor device includes a MISFET. The semiconductor device also includes a silicon nitride film 12 and a silicon nitride film 10 arranged on the silicon nitride film 12. The silicon nitride film 12 covers at least a portion of an upper part of a source/drain 8 of the MISFET and has a film thickness thinner than a height of a gate electrode 4. The source/drain 8 includes nickel silicide 9 on its boundary to the silicon nitride film 10. The silicon nitride film 10 is a stressed film. A tight adhering property between the silicon nitride film 12 and the surface of the source/drain 8 and that between the silicon nitride film 12 and the silicon nitride film 10 are rendered higher than a tight adhering property which would prevail when the silicon nitride film 10 be made to adhere tightly to the source/drain 8.Type: ApplicationFiled: February 29, 2012Publication date: July 19, 2012Applicants: RENESAS ELECTRONICS CORPORATION, NEC CORPORATIONInventors: Kazuya UEJIMA, Hidetatsu NAKAMURA, Akihito SAKAKIDANI, Eiichirou WATANABE
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Publication number: 20120007194Abstract: A method of manufacturing N-type MOSFET includes: implanting a p-type dopant into in a surface layer of a semiconductor substrate to form a channel region; forming a gate insulating film including High-k material and a gate electrode on said channel region; implanting a p-type dopant into both ends of said channel region in an inner portion of said semiconductor substrate to form halo regions; implanting a p-type dopant into both ends of said channel region in a surface layer of said semiconductor substrate to form extension regions. One of said step of forming said channel region and said step of forming halo regions includes: implanting C into one of said channel region and said halo regions. An inclusion amount of said High-k material is an amount that increase of a threshold voltage caused by said High-k material being included in said gate insulating film compensates for decrease of said threshold voltage caused by said C being implanted.Type: ApplicationFiled: July 7, 2011Publication date: January 12, 2012Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Akihito SAKAKIDANI, Kiyotaka IMAI
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Publication number: 20100224941Abstract: A semiconductor device includes a MISFET. The semiconductor device also includes a silicon nitride film 12 and a silicon nitride film 10 arranged on the silicon nitride film 12. The silicon nitride film 12 covers at least a portion of an upper part of a source/drain 8 of the MISFET and has a film thickness thinner than a height of a gate electrode 4. The source/drain 8 includes nickel suicide 9 on its boundary to the silicon nitride film 10. The silicon nitride film 10 is a stressed film. A tight adhering property between the silicon nitride film 12 and the surface of the source/drain 8 and that between the silicon nitride film 12 and the silicon nitride film 10 are rendered higher than a tight adhering property which would prevail when the silicon nitride film 10 be made to adhere tightly to the source/drain 8.Type: ApplicationFiled: June 5, 2007Publication date: September 9, 2010Applicants: NEC CORPORATION, NEC ELECTRONICS CORPORATIONInventors: Kazuya Uejima, Hidetatsu Nakamura, Akihito Sakakidani, Eiichirou Watanabe
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Publication number: 20090319971Abstract: An exemplary aspect of an embodiment of the present Invention is a method of verifying a layout for a semiconductor integrated circuit device including: segmenting a layout of a semiconductor integrated circuit device into a plurality of local regions; calculating a ratio for each local region, the ratio being the area of a region in which an element isolation layer is exposed on a semiconductor wafer surface forming the semiconductor integrated circuit device to the area of the local region; and verifying the layout of the semiconductor integrated circuit device based on the ratio.Type: ApplicationFiled: June 15, 2009Publication date: December 24, 2009Applicant: NEC ELECTRONICS CORPORATIONInventor: Akihito SAKAKIDANI
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Patent number: 7439124Abstract: Method of manufacturing a semiconductor device includes: forming a substrate protection film to cover an n-type FET forming region having a first gate electrode and a p-type FET forming region having a second gate electrode; opening the p-type FET forming region by patterning a resist film after the resist film is formed to cover the n-type FET and p-type FET forming regions; exposing the surface of the semiconductor substrate by selectively removing the substrate protection film in the p-type FET forming region, leaving the film only on side walls of the second gate electrode; forming a pair of p-type extension regions at both sides of the second gate electrode, by doping impurities to the semiconductor substrate, with the resist film, the second gate electrode, and the substrate protection film formed on side walls of the second electrode; and removing the resist film formed on the n-type FET forming region.Type: GrantFiled: April 11, 2006Date of Patent: October 21, 2008Assignee: NEC Electronics CorporationInventors: Toshinori Fukai, Akihito Sakakidani
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Publication number: 20060226558Abstract: Method of manufacturing a semiconductor device includes: forming a substrate protection film to cover an n-type FET forming region having a first gate electrode and a p-type FET forming region having a second gate electrode; opening the p-type FET forming region by patterning a resist film after the resist film is formed to cover the n-type FET and p-type FET forming regions; exposing the surface of the semiconductor substrate by selectively removing the substrate protection film in the p-type FET forming region, leaving the film only on side walls of the second gate electrode; forming a pair of p-type extension regions at both sides of the second gate electrode, by doping impurities to the semiconductor substrate, with the resist film, the second gate electrode, and the substrate protection film formed on side walls of the second electrode; and removing the resist film formed on the n-type FET forming region.Type: ApplicationFiled: April 11, 2006Publication date: October 12, 2006Applicant: NEC ELECTRONICS CORPORATIONInventors: Toshinori Fukai, Akihito Sakakidani
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Publication number: 20050250259Abstract: In a silicon-on-insulator (SOI)-type semiconductor device, a buried silicon dioxide layer is produced in the silicon substrate. An area of the silicon substrate, which is sited above the buried silicon dioxide layer, is defined as an SOI area, and the remaining area is defined as a non-SOI area. A peripheral edge portion of the buried silicon dioxide layer is formed as a swelling edge portion. A first field-isolation layer is formed at the SOI area along the swelling edge portion of the buried silicon dioxide layer, a second field-isolation layer is formed at the non-SOI area along the swelling edge portion of the buried silicon dioxide layer.Type: ApplicationFiled: March 16, 2005Publication date: November 10, 2005Applicant: NEC ELECTRONICS CORPORATIONInventors: Akihito Sakakidani, Takayuki Suzuki