Abstract: The present invention relates to an operation device which can be easily installed on a vehicle door, and a vehicle door comprising the operation device. An operation device of the present invention comprises: a gripper provided on an inner surface of a door of a vehicle; an operation interface provided on an inner side surface of the gripper for receiving an operation input entered by an occupant to operate at least one in-vehicle device; a first sensor provided on an outer side surface of the gripper for detecting a finger of the occupant; a second sensor provided on at least one of the inner side surface and an upper surface of the gripper for detecting a finger of the occupant; and a controller connected to the operation interface, the first sensor, the second sensor, and the at least one in-vehicle device.

Abstract: An image-recording apparatus includes: a first tank defining a first storage chamber; a second tank defining a second storage chamber; a conveying mechanism for conveying sheets along a conveying path extending in a depthwise direction and a widthwise direction perpendicular to a vertical direction and the depthwise direction; and a recording head including a nozzle. Liquid in the first storage chamber is supplied through a communication port to the second storage chamber and then to the recording head through a liquid outlet port. The second storage chamber is positioned further in a first depthwise direction relative to the nozzle and further in a first widthwise direction relative to the conveying path. A volume of a prescribed space above a liquid level equal to a height of the communication port in the second storage chamber is greater than that of a liquid channel between the liquid outlet port and the nozzle.

Abstract: To suppress short channel effects and obtain a high driving current by means of a semiconductor device having an MISFET wherein a material having high mobility and high dielectric constant, such as germanium, is used for a channel. A p-type well is formed on a surface of a p-type silicon substrate. A silicon germanium layer having a dielectric constant higher than that of the p-type silicon substrate is formed to have a thickness of 30 nm or less on the p-type well. Then, on the silicon germanium layer, a germanium layer having a dielectric constant higher than that of the silicon germanium layer is formed to have a thickness of 3-40 nm by epitaxial growing. The germanium layer is permitted to be a channel region; and a gate insulating film, a gate electrode, a side wall insulating film, an n-type impurity diffusion region and a silicide layer are formed.

Abstract: A semiconductor device includes a bonding pad, and an area designation marking, wherein the bonding pad includes a first region, a second region, and a third region placed between the first region and the second region, wherein the area designation marking includes a first area designation mark configured to designate a first boundary between the first region and the third region and a second area designation mark configured to designate a second boundary between the second region and the third region, wherein the first region and the second region are configured to be contacted with a test probe. The first area designation mark includes a first notch or a first protrusion. The second area designation mark includes a second notch or a second protrusion. The first area designation mark includes a first pair of notches that is linearly spaced apart from each other to designate the first boundary line.

Abstract: The lattice mismatching between a Ge layer and a Si layer is as large as about 4%. Thus, when the Ge layer is grown on the Si layer, penetration dislocation is introduced to cause leakage current at the p-i-n junction. Thereby, the photo-detection sensitivity is reduced, and the reliability of the element is also lowered. Further, in the connection with a Si waveguide, there are also problems of the reflection loss due to the difference in refractive index between Si and Ge, and of the absorption loss caused by a metal electrode.

Abstract: A semiconductor device includes a bonding pad, and an area designation marking, wherein the bonding pad includes a first region, a second region, and a third region placed between the first region and the second region, wherein the area designation marking includes a first area designation mark configured to designate a first boundary between the first region and the third region and a second area designation mark configured to designate a second boundary between the second region and the third region, wherein the first region and the second region are configured to be contacted with a test probe, The first area designation mark includes a first notch or a first protrusion. The second area designation mark includes a second notch or a second protrusion. The first area designation mark includes a first pair of notches that is linearly spaced apart from each other to designate the first boundary line.

Abstract: The semiconductor device having a bonding pad is provided. The bonding pad enables highly reliable connection and high flexibility of the selection of the area to be bonded. The semiconductor device includes a bonding pad and an area designation marking. The bonding pad includes a first region, a second region and a third region formed between the first region and the third region. The area designation marking includes a first notch for designating a first boundary of the first region and the third region and a second notch for designation a second boundary of the second region and the third region. Any of the first region and the second region can be used as the region where the scratch formed by a probing process is to be formed.

Abstract: The lattice mismatching between a Ge layer and a Si layer is as large as about 4%. Thus, when the Ge layer is grown on the Si layer, penetration dislocation is introduced to cause leakage current at the p-i-n junction. Thereby, the photo-detection sensitivity is reduced, and the reliability of the element is also lowered. Further, in the connection with a Si waveguide, there are also problems of the reflection loss due to the difference in refractive index between Si and Ge, and of the absorption loss caused by a metal electrode.

Abstract: An impact ionization MISFET includes: a gate insulating film which has one surface contacting the surface of a semiconductor substrate; a gate electrode that contacts the other surface of the gate insulating film; and a drain region, channel region, impact ionization region, and source region that are formed in one direction on the semiconductor substrate. The channel region is on the surface of the semiconductor substrate to which the gate insulating film is in contact, and a channel is generated when a voltage is applied to the gate electrode. When a voltage is applied between the drain region and the source region and when a channel is generated in the channel region, avalanche multiplication of carriers injected from the source region occurs in the impact ionization region. The flow path of the carriers between the channel and the source region occurs within the semiconductor substrate.

Abstract: To suppress short channel effects and obtain a high driving current by means of a semiconductor device having an MISFET wherein a material having high mobility and high dielectric constant, such as germanium, is used for a channel. A p-type well is formed on a surface of a p-type silicon substrate. A silicon germanium layer having a dielectric constant higher than that of the p-type silicon substrate is formed to have a thickness of 30 nm or less on the p-type well. Then, on the silicon germanium layer, a germanium layer having a dielectric constant higher than that of the silicon germanium layer is formed to have a thickness of 3-40 nm by epitaxial growing. The germanium layer is permitted to be a channel region; and a gate insulating film, a gate electrode, a side wall insulating film, an n-type impurity diffusion region and a silicide layer are formed.

Abstract: An objective of this invention is to allow each process of contacting of a test probe and bonding to be reliably conducted within a given region. A semiconductor device 100 has a probing mark 111 forming region; a bonding pad 110 having a bonding region 113; and a check mark 120 separate from the bonding pad 110. In the configuration, the probing mark 111 forming region and the bonding region 113 can be identified on the basis of a planar shape of the check mark 120.

Abstract: The semiconductor device having a bonding pad is provided. The bonding pad enables highly reliable connection and high flexibility of the selection of the area to be bonded. The semiconductor device includes a bonding pad and an area designation marking. The bonding pad includes a first region, a second region and a third region formed between the first region and the third region. The area designation marking includes a first notch for designating a first boundary of the first region and the third region and a second notch for designation a second boundary of the second region and the third region. Any of the first region and the second region can be used as the region where the scratch formed by a probing process is to be formed.

Abstract: An objective of this invention is to allow each process of contacting of a test probe and bonding to be reliably conducted within a given region. A semiconductor device 100 has a probing mark 111 forming region; a bonding pad 110 having a bonding region 113; and a check mark 120 separate from the bonding pad 110. In the configuration, the probing mark 111 forming region and the bonding region 113 can be identified on the basis of a planar shape of the check mark 120.

Abstract: A charge storing layer of a photodiode having an N-type conductivity includes an N+-type additional implant area in the vicinity of a junction between the charge storing layer and an isolation region. The additional implant area provides an increase of stored charge and suppression of increase of the pulse voltage for a substrate shutter, and can be made to have a smaller width within a current design rule.

Abstract: This invention provides a manufacturing process for a charge transfer device comprising an N-type well formed in a P-type well on a semiconductor substrate for transferring a signal charge, an N+ region formed on both sides along the charge transfer direction of the N-type well and containing a dopant in a higher concentration than that in the N-type well, a P-type region formed around the N+ region, and a gate electrode covering the N+ region and the N-type well and formed via a gate insulator, comprising ion-implanting an N-type dopant into the region to be the N-type well and the N+ region using the first mask and ion-implanting a P-type dopant into the region to be the N-type well using the second mask. Thus, there can be provided a charge transfer device which has a structure where there is an N+ region on both sides of the N-type well, a large maximum transferable charge and a compact CCD with a width up to 3 times the minimum design dimension.

Abstract: A solid state image pickup device has a photo diodes for producing charge packets from image-carrying light, a vertical overflow drain formed under the photo diodes, charge transfer channel regions selectively connected to the photo diodes through transfer gate transistors, resistive gate electrodes capacitively coupled to said charge transfer channel regions, respectively, and a pulse signal source connected to far ends of the resistive gate electrodes and near ends of the resistive gate electrodes closer to a horizontal charge transfer unit, and the pulse signal source produces a potential gradient in the charge transfer channel regions after transfer of the charge packets to the charge transfer channel regions so that the charge packets are conveyed through the horizontal charge transfer unit without a large horizontal charge transfer signal.

Abstract: A solid state image pickup device has a photo diodes for producing charge packets from image-carrying light, a vertical overflow drain formed under the photo diodes, charge transfer channel regions selectively connected to the photo diodes through transfer gate transistors, resistive gate electrodes capacitively coupled to said charge transfer channel regions, respectively, and a pulse signal source connected to far ends of the resistive gate electrodes and near ends of the resistive gate electrodes closer to a horizontal charge transfer unit, and the pulse signal source produces a potential gradient in the charge transfer channel regions after transfer of the charge packets to the charge transfer channel regions so that the charge packets are conveyed through the horizontal charge transfer unit without a large horizontal charge transfer signal.

Abstract: Disclosed is a photoelectric transducer having a photodiode that is formed on a second-conductivity-type well and is composed of a first-conductivity-type region to accumulate signal charge when light is supplied and a first second-conductivity-type region formed on the first-conductivity-type region. The first second-conductivity-type region is separated from a second-conductivity-type device separation region and is connected to the second-conductivity-type device separation region at part of the circumference of the first second-conductivity-type region through a second second-conductivity-type region that is formed to be at least partially shallower than the first second-conductivity-type region. Also, disclosed is a solid-state image sensing device equipped with the photoelectric transducer.

Abstract: A charge storing layer of a photodiode having an N-type conductivity includes an N30 -type additional implant area in the vicinity of a junction between the charge storing layer and an isolation region. The additional implant area provides an increase of stored charge and suppression of increase of the pulse voltage for a substrate shutter, and can be made to have a smaller width within a current design rule.

Abstract: This invention provides a manufacturing process for a charge transfer device comprising an N-type well formed in a P-type well on a semiconductor substrate for transferring a signal charge, an N+ region formed on both sides along the charge transfer direction of the N-type well and containing a dopant in a higher concentration than that in the N-type well, a P-type region formed around the N+ region, and a gate electrode covering the N+ region and the N-type well and formed via a gate insulator, comprising ion-implanting an N-type dopant into the region to be the N-type well and the N+ region using the first mask and ion-implanting a P-type dopant into the region to be the N-type well using the second mask. Thus, there can be provided a charge transfer device which has a structure where there is an N+ region on both sides of the N-type well, a large maximum transferable charge and a compact CCD with a width up to 3 times the minimum design dimension.