Patents by Inventor Akihito Tohata
Akihito Tohata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7978562Abstract: A semiconductor memory device operates by using a fixed power and a variable power. The device includes a plurality of word lines which select rows of a memory cell array, a plurality of word line drivers each of which is connected to a corresponding one of the word lines and includes a first CMOS gate, a first cutoff switch which is connected between a fixed power terminal and a power terminal of the first CMOS gate and cuts off the fixed power in a sleep mode, a switching circuit which is connected to the plurality of word lines and connects the plurality of word lines to a ground terminal in the sleep mode, and a power control circuit which generates the variable power by using the fixed power and sets the variable power to 0 V in the sleep mode.Type: GrantFiled: September 28, 2009Date of Patent: July 12, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Tomoaki Yabe, Akihito Tohata
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Patent number: 7791971Abstract: A semiconductor memory device includes first and second cell arrays which have memory cells arrayed in row and column directions, first and second bit lines which are connected to the memory cells arrayed in the column direction, and first and second sense amplifiers which are connected to the first, second bit lines, respectively. The device also includes first and second dummy cell arrays which have dummy cells arrayed in the row and column directions, a dummy word line which is connected to the dummy cells arrayed in the row direction, first and second dummy bit lines which are connected to the dummy cells arrayed in the column direction and receive an output from the dummy word line, and first and second sense amplifier activation circuits which activate the first, second sense amplifiers in accordance with first and second control signals output from the first and second dummy bit lines, respectively.Type: GrantFiled: April 27, 2009Date of Patent: September 7, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Akihito Tohata, Tomoaki Yabe
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Publication number: 20100014375Abstract: A semiconductor memory device operates by using a fixed power and a variable power. The device includes a plurality of word lines which select rows of a memory cell array, a plurality of word line drivers each of which is connected to a corresponding one of the word lines and includes a first CMOS gate, a first cutoff switch which is connected between a fixed power terminal and a power terminal of the first CMOS gate and cuts off the fixed power in a sleep mode, a switching circuit which is connected to the plurality of word lines and connects the plurality of word lines to a ground terminal in the sleep mode, and a power control circuit which generates the variable power by using the fixed power and sets the variable power to 0 V in the sleep mode.Type: ApplicationFiled: September 28, 2009Publication date: January 21, 2010Inventors: Tomoaki YABE, Akihito Tohata
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Patent number: 7606106Abstract: A semiconductor memory device operates by using a fixed power and a variable power. The device includes a plurality of word lines which select rows of a memory cell array, a plurality of word line drivers each of which is connected to a corresponding one of the word lines and includes a first CMOS gate, a first cutoff switch which is connected between a fixed power terminal and a power terminal of the first CMOS gate and cuts off the fixed power in a sleep mode, a switching circuit which is connected to the plurality of word lines and connects the plurality of word lines to a ground terminal in the sleep mode, and a power control circuit which generates the variable power by using the fixed power and sets the variable power to 0 V in the sleep mode.Type: GrantFiled: September 13, 2007Date of Patent: October 20, 2009Assignee: Kabushiki Kaisha ToshibaInventors: Tomoaki Yabe, Akihito Tohata
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Publication number: 20090213635Abstract: A semiconductor memory device includes first and second cell arrays which have memory cells arrayed in row and column directions, first and second bit lines which are connected to the memory cells arrayed in the column direction, and first and second sense amplifiers which are connected to the first, second bit lines, respectively. The device also includes first and second dummy cell arrays which have dummy cells arrayed in the row and column directions, a dummy word line which is connected to the dummy cells arrayed in the row direction, first and second dummy bit lines which are connected to the dummy cells arrayed in the column direction and receive an output from the dummy word line, and first and second sense amplifier activation circuits which activate the first, second sense amplifiers in accordance with first and second control signals output from the first and second dummy bit lines, respectively.Type: ApplicationFiled: April 27, 2009Publication date: August 27, 2009Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Akihito Tohata, Tomoaki Yabe
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Patent number: 7535784Abstract: A semiconductor memory device includes first and second cell arrays which have memory cells arrayed in row and column directions, first and second bit lines which are connected to the memory cells arrayed in the column direction, and first and second sense amplifiers which are connected to the first, second bit lines, respectively. The device also includes first and second dummy cell arrays which have dummy cells arrayed in the row and column directions, a dummy word line which is connected to the dummy cells arrayed in the row direction, first and second dummy bit lines which are connected to the dummy cells arrayed in the column direction and receive an output from the dummy word line, and first and second sense amplifier activation circuits which activate the first, second sense amplifiers in accordance with first and second control signals output from the first and second dummy bit lines, respectively.Type: GrantFiled: October 15, 2007Date of Patent: May 19, 2009Assignee: Kabushiki Kaisha ToshibaInventors: Akihito Tohata, Tomoaki Yabe
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Publication number: 20090090973Abstract: A semiconductor device includes a device isolation insulating film which is provided in a semiconductor substrate, and an insulated-gate field-effect transistor which is disposed adjacent to the device isolation insulating film in a gate length direction, the insulated-gate field-effect transistor including a gate insulation film which is provided on the semiconductor substrate, a gate electrode which is provided on the gate insulation film, a pair of impurity diffusion layers which are provided spaced apart in the semiconductor substrate in a manner to sandwich the gate electrode, and a redundant impurity diffusion layer which is provided between the device isolation insulating film and one of the pair of impurity diffusion layers.Type: ApplicationFiled: October 2, 2008Publication date: April 9, 2009Inventors: Akihito TOHATA, Osamu HIRABAYASHI
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Publication number: 20080089156Abstract: A semiconductor memory device includes first and second cell arrays which have memory cells arrayed in row and column directions, first and second bit lines which are connected to the memory cells arrayed in the column direction, and first and second sense amplifiers which are connected to the first, second bit lines, respectively. The device also includes first and second dummy cell arrays which have dummy cells arrayed in the row and column directions, a dummy word line which is connected to the dummy cells arrayed in the row direction, first and second dummy bit lines which are connected to the dummy cells arrayed in the column direction and receive an output from the dummy word line, and first and second sense amplifier activation circuits which activate the first, second sense amplifiers in accordance with first and second control signals output from the first and second dummy bit lines, respectively.Type: ApplicationFiled: October 15, 2007Publication date: April 17, 2008Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Akihito Tohata, Tomoaki Yabe
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Publication number: 20080068915Abstract: A semiconductor memory device operates by using a fixed power and a variable power. The device includes a plurality of word lines which select rows of a memory cell array, a plurality of word line drivers each of which is connected to a corresponding one of the word lines and includes a first CMOS gate, a first cutoff switch which is connected between a fixed power terminal and a power terminal of the first CMOS gate and cuts off the fixed power in a sleep mode, a switching circuit which is connected to the plurality of word lines and connects the plurality of word lines to a ground terminal in the sleep mode, and a power control circuit which generates the variable power by using the fixed power and sets the variable power to 0 V in the sleep mode.Type: ApplicationFiled: September 13, 2007Publication date: March 20, 2008Inventors: Tomoaki Yabe, Akihito Tohata