Patents by Inventor Akiihiro Yoshitake

Akiihiro Yoshitake has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Wiring graphic verification method, program and apparatus
    Patent number: 7120881
    Abstract: An edge extraction unit extracts vertical and horizontal wiring edges and slanted wiring edges from overall wiring graphics, and a wiring width classification unit executes a scaling process for the overall wiring graphics to classify the wiring graphics into wiring width ranges which are divided by a predefined reference wiring width. A vertical and horizontal wiring edge extraction unit extracts the vertical and horizontal wiring edges which are in contact with graphics classified into the wiring width ranges, and a vertical and horizontal wiring interval verification unit verifies intervals between the vertical and horizontal wiring edges and opposed edges to be verification counterparts based on a vertical and horizontal reference interval for each wiring width range.
    Type: Grant
    Filed: March 22, 2004
    Date of Patent: October 10, 2006
    Assignee: Fujitsu Limited
    Inventors: Chikaaki Kodama, Akiihiro Yoshitake
  • Wiring graphic verification method, program and apparatus
    Publication number: 20050005252
    Abstract: An edge extraction unit extracts vertical and horizontal wiring edges and slanted wiring edges from overall wiring graphics, and a wiring width classification unit executes a scaling process for the overall wiring graphics to classify the wiring graphics into wiring width ranges which are divided by a predefined reference wiring width. A vertical and horizontal wiring edge extraction unit extracts the vertical and horizontal wiring edges which are in contact with graphics classified into the wiring width ranges, and a vertical and horizontal wiring interval verification unit verifies intervals between the vertical and horizontal wiring edges and opposed edges to be verification counterparts based on a vertical and horizontal reference interval for each wiring width range.
    Type: Application
    Filed: March 22, 2004
    Publication date: January 6, 2005
    Applicant: FUJITSU LIMITED
    Inventors: Chikaaki Kodama, Akiihiro Yoshitake