Patents by Inventor Akiji Kudo

Akiji Kudo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor integrated circuit having terminal for measuring bump connection resistance and semiconductor device provided with the same
    Patent number: 7786478
    Abstract: An integrated circuit is formed in a chip. Positioning marks are provided on at least two of four regions respectively near four corners of a first main surface of the chip. Terminals are provided on the first main surface to measure bump connection resistance. The terminals adjoin the positioning marks respectively. A connection wire is provided in the chip. The connection wire is connected to the terminals electrically.
    Type: Grant
    Filed: June 22, 2009
    Date of Patent: August 31, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Akiji Kudo
  • SEMICONDUCTOR INTEGRATED CIRCUIT HAVING TERMINAL FOR MEASURING BUMP CONNECTION RESISTANCE AND SEMICONDUCTOR DEVICE PROVIDED WITH THE SAME
    Publication number: 20090315029
    Abstract: An integrated circuit is formed in a chip. Positioning marks are provided on at least two of four regions respectively near four corners of a first main surface of the chip. Terminals are provided on the first main surface to measure bump connection resistance. The terminals adjoin the positioning marks respectively. A connection wire is provided in the chip. The connection wire is connected to the terminals electrically.
    Type: Application
    Filed: June 22, 2009
    Publication date: December 24, 2009
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Akiji Kudo