Patents by Inventor Akiji Shibata

Akiji Shibata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20120002420
    Abstract: An LED module includes an electrical insulation material including a first surface having a total reflectivity of not less than 80% with respect to light with a wavelength of 450 nm, a via hole penetrating through the electrical insulation material, a wiring pattern on a second surface of the electrical insulation material, a metal filler formed in the via hole and electrically connected to the wiring pattern, and an LED chip bonded to a surface of the metal filler on the first surface of the electrical insulation material, and sealed with a resin.
    Type: Application
    Filed: June 22, 2011
    Publication date: January 5, 2012
    Applicant: HITACHI CABLE, LTD.
    Inventors: Noboru Imai, Masahiro Noguchi, Fumiya Isaka, Akiji Shibata, Yuzuru Ashidate, Aki Suzuki
  • Publication number: 20100171210
    Abstract: A semiconductor device has a semiconductor element; an interposer substrate having a wiring pattern electrically connected to the semiconductor element and an insulating substrate formed with the wiring pattern; a connection layer for adhering between the semiconductor element and the interposer substrate; and a solder ball external terminal arranged on the interposer substrate. The insulating substrate is folded in a portion mounted with the external terminal arranged on an outer side to the semiconductor element, and the unfolded and folded portions of the insulating substrate are opposite each other to form a gap therebetween.
    Type: Application
    Filed: March 16, 2010
    Publication date: July 8, 2010
    Inventors: Masayuki Hosono, Akiji Shibata, Kimio Inaba
  • Patent number: 7626126
    Abstract: A multilayer semiconductor device has plural semiconductor devices, each having a circuit board for a ball grid array and a semiconductor chip provided on the board. The semiconductor boards are bonded together by a reflow mounting process to use a solder ball for interlayer connection so as to form a multilayer structure. The plural semiconductor devices each have a projection for restricting inclination of the circuit board, and the projection is provided between neighboring two of the circuit boards.
    Type: Grant
    Filed: June 7, 2006
    Date of Patent: December 1, 2009
    Assignee: Hitachi Cable, Ltd.
    Inventors: Akiji Shibata, Kimio Inaba, Masayuki Hosono
  • Publication number: 20080116559
    Abstract: A semiconductor device has a semiconductor element; an interposer substrate having a wiring pattern electrically connected to the semiconductor element and an insulating substrate formed with the wiring pattern; a connection layer for adhering between the semiconductor element and the interposer substrate; and a solder ball external terminal arranged on the interposer substrate. The insulating substrate is folded in a portion mounted with the external terminal arranged on an outer side to the semiconductor element, and the unfolded and folded portions of the insulating substrate are opposite each other to form a gap therebetween.
    Type: Application
    Filed: November 8, 2007
    Publication date: May 22, 2008
    Inventors: Masayuki Hosono, Akiji Shibata, Kimio Inaba
  • Patent number: 7355278
    Abstract: A technology is provided that can seal the opening in a wiring board using a transfer mold insulating resin from the opening. A mold die is used which includes a first die having a recess in a predetermined form and a second flat die. The first die is disposed on a surface of a wiring board which has a plurality of openings and on which a semiconductor chip is mounted via an elastic material. The second die is disposed on a back surface of the wiring board opposite the surface on which the semiconductor chip is mounted. The mold is used for sealing with an insulating resin the periphery of the semiconductor chip and at least one of the openings of the wiring board, wherein the above-described second die has a protrusion around an area overlapping the opening to be sealed with the insulating resin.
    Type: Grant
    Filed: March 11, 2004
    Date of Patent: April 8, 2008
    Assignee: Hitachi Cable, Ltd.
    Inventors: Akiji Shibata, Akihiro Okamoto, Yosuke Shimazaki, Kazumoto Komiya
  • Publication number: 20070151754
    Abstract: A multilayer semiconductor device has plural semiconductor devices, each having a circuit board for a ball grid array and a semiconductor chip provided on the board. The semiconductor boards are bonded together by a reflow mounting process to use a solder ball for interlayer connection so as to form a multilayer structure. The plural semiconductor devices each have a projection for restricting inclination of the circuit board, and the projection is provided between neighboring two of the circuit boards.
    Type: Application
    Filed: June 7, 2006
    Publication date: July 5, 2007
    Applicant: HITACHI CABLE, LTD.
    Inventors: Akiji Shibata, Kimio Inaba, Masayuki Hosono
  • Patent number: 7213335
    Abstract: The amount of time required to manufacture double-sided printed circuit boards that contain conductor bridges can be reduced. A method is provided which includes the steps of forming holes which pass through an insulating board and a first conductor layer formed on a first main side of the insulating board, bonding a second conductor layer to a second main side of the insulating board having the holes, forming a third conductor layer on the whole first main side of the insulating board after bonding the second conductor layer, masking preset holes with a plating resist, plating the first conductor and holes in the insulating board, patterning the first conductor layer to form a first conductor pattern, patterning said second conductor layer to form a second conductor pattern, and removing the plating resist and the third conductor layer from an area which is covered with the plating resist.
    Type: Grant
    Filed: March 1, 2004
    Date of Patent: May 8, 2007
    Assignee: Hitachi Cable, Ltd.
    Inventors: Akiji Shibata, Toyoharu Koizumi, Tsuyoshi Ishihara, Takashi Sato
  • Patent number: 6940161
    Abstract: In a semiconductor device comprising: a wiring board comprising a conductor wiring having a predetermined pattern provided on the surface of an insulating substrate; an elastomer provided on the wiring board; a semiconductor chip bonded onto the wiring board through the elastomer; and an insulator for sealing the periphery of the semiconductor chip and the elastomer, the semiconductor chip in its external terminal being electrically connected to the conductor wiring, a part of the elastomer is exposed onto the surface of the insulator. By virtue of the above construction, a lowering in device reliability can be prevented.
    Type: Grant
    Filed: May 22, 2002
    Date of Patent: September 6, 2005
    Assignee: Hitachi Cable, Ltd.
    Inventors: Tadashi Kawanobe, Yasuharu Kameyama, Masayuki Hosono, Kazumoto Komiya, Akiji Shibata
  • Publication number: 20040180475
    Abstract: An object of the present invention is to provide a technology that can seal the opening of the interposer by transfer mold with the leak of the insulating resin from the above-described opening prevented.
    Type: Application
    Filed: March 11, 2004
    Publication date: September 16, 2004
    Inventors: Akiji Shibata, Akihiro Okamoto, Yosuke Shimazaki, Kazumoto Komiya
  • Publication number: 20040172814
    Abstract: This invention reduces the amount of time required to manufacture double-sided printed circuit boards that contain conductor bridges.
    Type: Application
    Filed: March 1, 2004
    Publication date: September 9, 2004
    Inventors: Akiji Shibata, Toyoharu Koizumi, Tsuyoshi Ishihara, Takashi Sato
  • Publication number: 20020185661
    Abstract: In a semiconductor device comprising: a wiring board comprising a conductor wiring having a predetermined pattern provided on the surface of an insulating substrate; an elastomer provided on the wiring board; a semiconductor chip bonded onto the wiring board through the elastomer; and an insulator for sealing the periphery of the semiconductor chip and the elastomer, the semiconductor chip in its external terminal being electrically connected to the conductor wiring, a part of the elastomer is exposed onto the surface of the insulator. By virtue of the above construction, a lowering in device reliability can be prevented.
    Type: Application
    Filed: May 22, 2002
    Publication date: December 12, 2002
    Applicant: HITACHI CABLE,LTD.
    Inventors: Tadashi Kawanobe, Yasuharu Kameyama, Masayuki Hosono, Kazumoto Komiya, Akiji Shibata
  • Patent number: 5182667
    Abstract: A method of receiving wavelength multiplex signals is designed to receive together, at an end of an optical fiber transmission path, optical information signals transmitted in multiple wavelengths, which correspond to multiple kinds of information, from a plurality of information sources distributed at a virtually constant interval along the transmission path in response to an optical trigger signal. Each of the optical information signals is sampled at a time interval that is in inverse proportion to the light velocity which depends on the wavelength of the signal, so that the content, kind and source of information are identified at the signal reception.
    Type: Grant
    Filed: May 16, 1991
    Date of Patent: January 26, 1993
    Assignee: Hitachi Cable Limited
    Inventors: Akiji Shibata, Nobuo Ando