Patents by Inventor Akiko Masada

Akiko Masada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor device including a gate insulating film having a metal oxide layer having trap levels
    Patent number: 8476718
    Abstract: A semiconductor device includes a MISFET comprising: a semiconductor layer including a semiconductor region formed therein; a gate insulating film formed above the semiconductor region, and including a metal oxide layer containing a metal and oxygen, the metal contained in the metal oxide layer being at least one selected from Hf and Zr, the metal oxide layer further including at least one element selected from the group consisting of Ru, Cr, Os, V, Tc, and Nb, the metal oxide layer having sites that capture or release charges formed by inclusion of the element, density of the element in the metal oxide layer being in the range of 1×1015 cm?3 to 2.96×1020 cm?3, the sites being distributed to have a peak closer to the semiconductor region than to a center of the metal oxide layer; and a gate electrode formed on the gate insulating film.
    Type: Grant
    Filed: February 23, 2010
    Date of Patent: July 2, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Izumi Hirano, Yuichiro Mitani, Tatsuo Shimizu, Yasushi Nakasaki, Akiko Masada, Shigeto Fukatsu, Masahiro Koike
  • SEMICONDUCTOR DEVICE
    Publication number: 20100244157
    Abstract: A semiconductor device includes a MISFET comprising: a semiconductor layer including a semiconductor region formed therein; a gate insulating film formed above the semiconductor region, and including a metal oxide layer containing a metal and oxygen, the metal contained in the metal oxide layer being at least one selected from Hf and Zr, the metal oxide layer further including at least one element selected from the group consisting of Ru, Cr, Os, V, Tc, and Nb, the metal oxide layer having sites that capture or release charges formed by inclusion of the element, density of the element in the metal oxide layer being in the range of 1×1015 cm?3 to 2.96×1020 cm?3, the sites being distributed to have a peak closer to the semiconductor region than to a center of the metal oxide layer; and a gate electrode formed on the gate insulating film.
    Type: Application
    Filed: February 23, 2010
    Publication date: September 30, 2010
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Izumi HIRANO, Yuichiro Mitani, Tatsuo Shimizu, Yasushi Nakasaki, Akiko Masada, Shigeto Fukatsu, Masahiro Koike