Patents by Inventor Akiko Nomachi
Akiko Nomachi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220399275Abstract: A semiconductor memory device includes: a stacked structure including first layers including conductive layers disposed in a first and a third regions and insulating layers disposed in a second region, first to third insulating members extending in a stacking direction, semiconductor layers disposed in the first and the third regions, and a contact electrode disposed in the second region. The first and the third insulating members extend across the first to third regions and the second insulating member extends across the first and the third regions. The second insulating member contacts the insulating layers. The first layers extend in a direction in the second region from a side of the first insulating member to a side of the third insulating member. The conductive layers in the first and the third regions are mutually connected via conductive layers in the second region.Type: ApplicationFiled: December 13, 2021Publication date: December 15, 2022Applicant: Kioxia CorporationInventors: So HIKOSAKA, Akiko NOMACHI, Osamu MATSUURA
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Patent number: 9780104Abstract: An embodiment includes: a semiconductor substrate, a memory cell array region including a plurality of conductive layers connected to memory cells arranged in a stacking direction on the semiconductor substrate; a peripheral region including a transistor on the substrate; a plurality of first layers and second layers stacked alternately in the stacking direction, above the transistor; and a plurality of first contacts penetrating the plurality of first and second layers and connected to the transistor. The plurality of first layers and second layers are stacked alternately in the stacking direction, above the transistor disposed in the peripheral region. A plurality of contacts penetrating the plurality of first layers and second layers are connected to the transistor. Moreover, the first layer mainly contains a different material from the second layer.Type: GrantFiled: March 16, 2016Date of Patent: October 3, 2017Assignee: TOSHIBA MEMORY CORPORATIONInventors: Akiko Nomachi, Hisashi Kato
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Publication number: 20170077113Abstract: An embodiment includes: a semiconductor substrate, a memory cell array region including a plurality of conductive layers connected to memory cells arranged in a stacking direction on the semiconductor substrate; a peripheral region including a transistor on the substrate ; a plurality of first layers and second layers stacked alternately in the stacking direction, above the transistor; and a plurality of first contacts penetrating the plurality of first and second layers and connected to the transistor. The plurality of first layers and second layers are stacked alternately in the stacking direction, above the transistor disposed in the peripheral region. A plurality of contacts penetrating the plurality of first layers and second layers are connected to the transistor. Moreover, the first layer mainly contains a different material from the second layer.Type: ApplicationFiled: March 16, 2016Publication date: March 16, 2017Applicant: Kabushiki Kaisha ToshibaInventors: Akiko NOMACHI, Hisashi KATO
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Patent number: 9520339Abstract: According to one embodiment, a semiconductor device includes a semiconductor substrate having a first surface and a second surface, and having a LSI on the first surface of the semiconductor substrate, a first insulating layer with an opening, the first insulating layer provided on the first surface of the semiconductor substrate, a conductive layer on the opening, the conductive layer being connected to the LSI, and a via extending from a second surface of the semiconductor substrate to the conductive layer through the opening, the via having a size larger than a size of the opening in a range from the second surface to a first interface between the semiconductor substrate and the first insulating layer, and having a size equal to the size of the opening in the opening.Type: GrantFiled: February 5, 2015Date of Patent: December 13, 2016Assignee: KABUSHIKI KAISHA TOSHIBAInventor: Akiko Nomachi
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Patent number: 9190607Abstract: According to one embodiment, a magnetoresistive element manufacturing method is provided. In this magnetoresistive element manufacturing method, a first ferromagnetic layer, tunnel barrier layer, and second ferromagnetic layer are sequentially formed on a substrate. A conductive hard mask is formed on the second ferromagnetic layer. The hard mask is patterned. A hard layer is formed on the side surface of the hard mask. The second ferromagnetic layer, tunnel barrier layer, and first ferromagnetic layer are processed by IBE in an oblique direction by using the hard mask and hard layer as masks. The IBE etching rate of the hard layer is lower than that of the hard mask.Type: GrantFiled: February 11, 2014Date of Patent: November 17, 2015Assignee: KABUSHIKI KAISHA TOSHIBAInventor: Akiko Nomachi
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Publication number: 20150155223Abstract: According to one embodiment, a semiconductor device includes a semiconductor substrate having a first surface and a second surface, and having a LSI on the first surface of the semiconductor substrate, a first insulating layer with an opening, the first insulating layer provided on the first surface of the semiconductor substrate, a conductive layer on the opening, the conductive layer being connected to the LSI, and a via extending from a second surface of the semiconductor substrate to the conductive layer through the opening, the via having a size larger than a size of the opening in a range from the second surface to a first interface between the semiconductor substrate and the first insulating layer, and having a size equal to the size of the opening in the opening.Type: ApplicationFiled: February 5, 2015Publication date: June 4, 2015Inventor: Akiko NOMACHI
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Patent number: 8803123Abstract: According to one embodiment, a resistance change memory includes resistance change elements arrayed with a first space in a first direction and with a second space wider than the first space in a second direction orthogonal to the first direction, second conductive layers disposed on sidewalls of the resistance change elements, each of the second conductive layers having a width greater than or equal to a half of the first space in the first direction and having a width less than a half of the second space in the second direction, the second conductive layers functioning as a first bit line extending in the first direction, a second insulating layer disposed on a sidewall of the first bit line, and not filling the second space, and a third conductive layer functioning as a second bit line extending in the first direction by filling the second space.Type: GrantFiled: March 14, 2013Date of Patent: August 12, 2014Assignee: Kabushiki Kaisha ToshibaInventor: Akiko Nomachi
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Publication number: 20140159176Abstract: According to one embodiment, a magnetoresistive element manufacturing method is provided. In this magnetoresistive element manufacturing method, a first ferromagnetic layer, tunnel barrier layer, and second ferromagnetic layer are sequentially formed on a substrate. A conductive hard mask is formed on the second ferromagnetic layer. The hard mask is patterned. A hard layer is formed on the side surface of the hard mask. The second ferromagnetic layer, tunnel barrier layer, and first ferromagnetic layer are processed by IBE in an oblique direction by using the hard mask and hard layer as masks. The IBE etching rate of the hard layer is lower than that of the hard mask.Type: ApplicationFiled: February 11, 2014Publication date: June 12, 2014Applicant: Kabushiki Kaisha ToshibaInventor: Akiko NOMACHI
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Patent number: 8691596Abstract: According to one embodiment, a magnetoresistive element manufacturing method is provided. In this magnetoresistive element manufacturing method, a first ferromagnetic layer, tunnel barrier layer, and second ferromagnetic layer are sequentially formed on a substrate. A conductive hard mask is formed on the second ferromagnetic layer. The hard mask is patterned. A hard layer is formed on the side surface of the hard mask. The second ferromagnetic layer, tunnel barrier layer, and first ferromagnetic layer are processed by IBE in an oblique direction by using the hard mask and hard layer as masks. The IBE etching rate of the hard layer is lower than that of the hard mask.Type: GrantFiled: September 5, 2012Date of Patent: April 8, 2014Assignee: Kabushiki Kaisha ToshibaInventor: Akiko Nomachi
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Patent number: 8637380Abstract: According to one embodiment, a method of manufacturing a semiconductor device including forming a metal film on aback surface of a glass substrate which supports a semiconductor substrate on a front surface thereof; forming a metal oxide film by oxidizing the whole or at least a portion of the metal film from the front surface; forming protective film, such as silicon nitride, on the metal oxide film; holding the front surface of the protective film with an electrostatic chuck; and forming a via for electrical connection in the semiconductor substrate while the front surface of the protective film is in contact with by the electrostatic chuck; then using a laser to delaminate the glass substrate from the semiconductor substrate.Type: GrantFiled: September 7, 2012Date of Patent: January 28, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Atsuko Sakata, Kazuyuki Higashi, Akiko Nomachi, Takeshi Ishizaki
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Publication number: 20130334487Abstract: According to one embodiment, a resistance change memory includes resistance change elements arrayed with a first space in a first direction and with a second space wider than the first space in a second direction orthogonal to the first direction, second conductive layers disposed on sidewalls of the resistance change elements, each of the second conductive layers having a width greater than or equal to a half of the first space in the first direction and having a width less than a half of the second space in the second direction, the second conductive layers functioning as a first bit line extending in the first direction, a second insulating layer disposed on a sidewall of the first bit line, and not filling the second space, and a third conductive layer functioning as a second bit line extending in the first direction by filling the second space.Type: ApplicationFiled: March 14, 2013Publication date: December 19, 2013Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Akiko NOMACHI
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Patent number: 8592882Abstract: According to one embodiment, there is disclosed a magnetic random access memory comprising: a semiconductor substrate; a selective transistor formed at the surface region of the semiconductor substrate and having a gate electrode, a gate insulating film, a source and a drain; and a magnetoresistive element formed on the drain including a magnetic storage layer in which a magnetization direction is variable, a magnetic reference layer in which a magnetization direction is fixed, and a nonmagnetic layer sandwiched between the magnetic storage layer and the magnetic reference layer.Type: GrantFiled: September 16, 2011Date of Patent: November 26, 2013Assignee: Kabushiki Kaisha ToshibaInventor: Akiko Nomachi
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Publication number: 20130252421Abstract: According to one embodiment, a method of manufacturing a semiconductor device including forming a metal film on aback surface of a glass substrate which supports a semiconductor substrate on a front surface thereof; forming a metal oxide film by oxidizing the whole or at least a portion of the metal film from the front surface; forming protective film, such as silicon nitride, on the metal oxide film; holding the front surface of the protective film with an electrostatic chuck; and forming a via for electrical connection in the semiconductor substrate while the front surface of the protective film is in contact with by the electrostatic chuck; then using a laser to delaminate the glass substrate from the semiconductor substrate.Type: ApplicationFiled: September 7, 2012Publication date: September 26, 2013Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Atsuko Sakata, Kazuyuki Higashi, Akiko Nomachi, Takeshi Ishizaki
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Publication number: 20130241015Abstract: According to one embodiment, a magnetoresistive element manufacturing method is provided. In this magnetoresistive element manufacturing method, a first ferromagnetic layer, tunnel barrier layer, and second ferromagnetic layer are sequentially formed on a substrate. A conductive hard mask is formed on the second ferromagnetic layer. The hard mask is patterned. A hard layer is formed on the side surface of the hard mask. The second ferromagnetic layer, tunnel barrier layer, and first ferromagnetic layer are processed by IBE in an oblique direction by using the hard mask and hard layer as masks. The IBE etching rate of the hard layer is lower than that of the hard mask.Type: ApplicationFiled: September 5, 2012Publication date: September 19, 2013Inventor: Akiko NOMACHI
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Publication number: 20130099349Abstract: According to one embodiment, a semiconductor device includes a semiconductor substrate having a first surface and a second surface, and having a LSI on the first surface of the semiconductor substrate, a first insulating layer with an opening, the first insulating layer provided on the first surface of the semiconductor substrate, a conductive layer on the opening, the conductive layer being connected to the LSI, and a via extending from a second surface of the semiconductor substrate to the conductive layer through the opening, the via having a size larger than a size of the opening in a range from the second surface to a first interface between the semiconductor substrate and the first insulating layer, and having a size equal to the size of the opening in the opening.Type: ApplicationFiled: August 24, 2012Publication date: April 25, 2013Inventor: Akiko Nomachi
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Patent number: 8339834Abstract: According to one embodiment, a non-volatile semiconductor memory device includes: a first line; a second line intersecting with the first line; and a memory cell arranged at a position where the second line intersects with the first line, wherein, the memory cell includes: a variable resistance element; and a negative resistance element connected in series to the variable resistance element.Type: GrantFiled: September 15, 2010Date of Patent: December 25, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Tsukasa Nakai, Yasuhiro Nojiri, Shuichi Kuboi, Motoya Kishida, Akiko Nomachi, Masanobu Baba, Hiroyuki Fukumizu
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Publication number: 20120187456Abstract: According to one embodiment, there is disclosed a magnetic random access memory comprising: a semiconductor substrate; a selective transistor formed at the surface region of the semiconductor substrate and having a gate electrode, a gate insulating film, a source and a drain; and a magnetoresistive element formed on the drain including a magnetic storage layer in which a magnetization direction is variable, a magnetic reference layer in which a magnetization direction is fixed, and a nonmagnetic layer sandwiched between the magnetic storage layer and the magnetic reference layer.Type: ApplicationFiled: September 16, 2011Publication date: July 26, 2012Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Akiko Nomachi
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Publication number: 20110205781Abstract: According to one embodiment, a non-volatile semiconductor memory device includes: a first line; a second line intersecting with the first line; and a memory cell arranged at a position where the second line intersects with the first line, wherein, the memory cell includes: a variable resistance element; and a negative resistance element connected in series to the variable resistance element.Type: ApplicationFiled: September 15, 2010Publication date: August 25, 2011Applicant: Kabushiki Kaisha ToshibaInventors: Tsukasa Nakai, Yasuhiro Nojiri, Shuichi Kuboi, Motoya Kishida, Akiko Nomachi, Masanobu Baba, Hiroyuki Fukumizu
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Patent number: 7875512Abstract: According to an aspect of the present invention, there is provided a method for manufacturing a semiconductor device, the method including: forming a first region and a second region in a semiconductor substrate by forming an element isolation region; forming an insulating film on the semiconductor substrate in the first region and the second region; forming a first metal film on the insulating film in the first region and in the second region; removing the first metal film in the second region; forming a second metal film on the first metal film in the first region and on the insulating film in the second region; and flattening top surfaces in the first region and the second region by performing a flattening process.Type: GrantFiled: January 16, 2009Date of Patent: January 25, 2011Assignee: Kabushiki Kaisha ToshibaInventor: Akiko Nomachi
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Publication number: 20090186472Abstract: According to an aspect of the present invention, there is provided a method for manufacturing a semiconductor device, the method including: forming a first region and a second region in a semiconductor substrate by forming an element isolation region; forming an insulating film on the semiconductor substrate in the first region and the second region; forming a first metal film on the insulating film in the first region and in the second region; removing the first metal film in the second region; forming a second metal film on the first metal film in the first region and on the insulating film in the second region; and flattening top surfaces in the first region and the second region by performing a flattening process.Type: ApplicationFiled: January 16, 2009Publication date: July 23, 2009Inventor: Akiko Nomachi