Abstract: A display device (100) includes a spontaneous light emission-type display panel (10). The display device includes a plurality of pixels (P). The plurality of pixels each include a plurality of sub pixels including a red sub pixel (R), a green sub pixel (G) and a blue sub pixel (B). The display panel includes a red light emitting element (1r), a green light emitting element (1g), and a blue light emitting element (1b). Red light, green light and blue light respectively emitted by the red light emitting element, the green light emitting element and the blue light emitting element each have a spectrum half width of 10 nm or less. The plurality of sub pixels included in each pixel further include a yellow sub pixel (Ye). The display panel further includes a yellow light emitting element (1y) provided in an area corresponding to the yellow sub pixel. The yellow light emitting element emits yellow light having a dominant wavelength of 550 nm or greater and 600 nm or less.

Abstract: A display device (100) includes a spontaneous light emission-type display panel (10). The display device includes a plurality of pixels (P). The plurality of pixels each include a plurality of sub pixels including a red sub pixel (R), a green sub pixel (G) and a blue sub pixel (B). The display panel includes a red light emitting element (1r), a green light emitting element (1g), and a blue light emitting element (1b). Red light, green light and blue light respectively emitted by the red light emitting element, the green light emitting element and the blue light emitting element each have a spectrum half width of 10 nm or less. The plurality of sub pixels included in each pixel further include a yellow sub pixel (Ye). The display panel further includes a yellow light emitting element (1y) provided in an area corresponding to the yellow sub pixel. The yellow light emitting element emits yellow light having a dominant wavelength of 550 nm or greater and 600 nm or less.

Abstract: An image processor (10) according to the present invention includes: a luminance segmentation section (12) arranged to segment an input image into a plurality of regions having different luminance levels from one another; a spatial frequency calculation section (14) arranged to calculate a spatial frequency of each of the plurality of regions; a contrast adjustment section (16) arranged to adjust a contrast of each of the plurality of regions based on the luminance level and the spatial frequency calculated by the spatial frequency calculation section (14); and a merging section (18) arranged to merge the plurality of regions, whose contrasts have been adjusted by the contrast adjustment section (16), into one image.

Abstract: A verification apparatus that verifies whether a reference circuit and an implemented circuit are logically equivalent deletes, respectively therefrom, all buffers and an even number of inverters between flip-flops. On each of the circuits, the apparatus further deletes and merges a flip-flop to another flip-flop that is logically equivalent. The name of the deleted flip-flip is added to the name of the flip-flop to which it is merged. The apparatus compares all of the names of the flip-flops and pairs the flip-flops by name. From the input pin of each of the paired flip-flops, logic cones are defined and using these logic cones, comparison of and verification between the reference circuit and the implemented circuit is performed.

Abstract: A verification apparatus that verifies whether a reference circuit and an implemented circuit are logically equivalent deletes, respectively therefrom, all buffers and an even number of inverters between flip-flops. On each of the circuits, the apparatus further deletes and merges a flip-flop to another flip-flop that is logically equivalent. The name of the deleted flip-flip is added to the name of the flip-flop to which it is merged. The apparatus compares all of the names of the flip-flops and pairs the flip-flops by name. From the input pin of each of the paired flip-flops, logic cones are defined and using these logic cones, comparison of and verification between the reference circuit and the implemented circuit is performed.

Abstract: Data in a data base that describe a logic circuit are converted to a simulation model, and simulations are performed based on them. When it is desired to change a part of the circuit while a simulation is in progress, a tentative correction is made by directly changing the simulation model without entering logics to the data base again. Simulation is continued based on the changed simulation model, then, after the action has been confirmed, the contents of the change are reflected on the data base. In this way, a circuit can easily be changed while simulation is in progress.

Abstract: An interactive logic simulation system includes a setting unit for setting at least one display format for logic simulation result information in the form of a window defined by an arbitrary display range by interacting with a user through a display screen; a first management table for managing the display mode of a free-format display format set by the setting unit; a second management table for managing the display mode of a stream display format as a time series display format of the logic simulation result information; a third management table for managing time series data of signal values for each signal terminal constituting the logic simulation result information; and a result display control unit for specifying the logic simulation result information by using management data from the first, second and third management tables, and for displaying the logic simulation result information so specified on the display screen.