Patents by Inventor Akiko Sekihara
Akiko Sekihara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 10403642Abstract: A semiconductor device includes a semiconductor layer, a first conductive layer, a tunneling insulating film, and a charge trapping film. The tunneling insulating film is provided between the semiconductor layer and the first conductive layer. The charge trapping film is provided between the first conductive layer and the tunneling insulating film. The charge trapping film includes a first separation layer, a first trapping layer, and a second trapping layer. The first trapping layer is positioned between the tunneling insulating film and the first separation layer. The second trapping layer is positioned between the first conductive layer and the first separation layer. A trapping efficiency of charge in the first trapping layer is higher than a trapping efficiency of charge in the second trapping layer.Type: GrantFiled: August 7, 2018Date of Patent: September 3, 2019Assignee: TOSHIBA MEMORY CORPORATIONInventors: Kazuhiro Matsuo, Akiko Sekihara, Akira Takashima, Tomonori Aoyama, Tatsunori Isogai, Masaki Noguchi
-
Publication number: 20190139981Abstract: A semiconductor device includes a semiconductor layer, a first conductive layer, a tunneling insulating film, and a charge trapping film. The tunneling insulating film is provided between the semiconductor layer and the first conductive layer. The charge trapping film is provided between the first conductive layer and the tunneling insulating film. The charge trapping film includes a first separation layer, a first trapping layer, and a second trapping layer. The first trapping layer is positioned between the tunneling insulating film and the first separation layer. The second trapping layer is positioned between the first conductive layer and the first separation layer. A trapping efficiency of charge in the first trapping layer is higher than a trapping efficiency of charge in the second trapping layer.Type: ApplicationFiled: August 7, 2018Publication date: May 9, 2019Applicant: TOSHIBA MEMORY CORPORATIONInventors: Kazuhiro Matsuo, Akiko Sekihara, Akira Takashima, Tomonori Aoyama, Tatsunori Isogai, Masaki Noguchi
-
Publication number: 20140284676Abstract: Plural first charge accumulation layers are arranged on a first gate-insulating film, and divided in the first direction and the second direction. Plural second charge accumulation layers are arranged on a second gate-insulating film and divided in the first direction and the second direction. An intermediate insulating film is arranged on the side surface of the first charge accumulation layers and on the side surface of the second charge accumulation layers. The control electrode includes a side-surface portion, which is arranged on the side surface of the intermediate insulating film, extends in the second direction, and faces via the intermediate insulating film to the side surface of the first charge accumulation layer and the side surface of the second charge accumulation layer, and a pad portion arranged monolithically on the lower portion of the side-surface portion and having a width larger than the film thickness of the side-surface portion.Type: ApplicationFiled: September 3, 2013Publication date: September 25, 2014Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Jungo INABA, Satoshi NAGASHIMA, Naoki KAI, Akiko SEKIHARA, Karin TAKAYAMA
-
Patent number: 8253189Abstract: A semiconductor device includes a semiconductor region, a tunnel insulating film formed on a surface of the semiconductor region, a charge-storage insulating film formed on a surface of the tunnel insulating film and containing silicon and nitrogen, a block insulating film formed on a surface of the charge-storage insulating film, and a control gate electrode formed on a surface of the block insulating film, wherein the tunnel insulating film has a first insulating film formed on the surface of the semiconductor region and containing silicon and oxygen, a second insulating film formed on a surface of the first insulating film, and a third insulating film formed on a surface of the second insulating film and containing silicon and oxygen, and a charge trap state in the second insulating film has a lower density than that in the charge-storage insulating film.Type: GrantFiled: July 28, 2009Date of Patent: August 28, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Katsuyuki Sekine, Akiko Sekihara, Kensuke Takano, Yoshio Ozawa
-
Publication number: 20110073935Abstract: In one embodiment, a non-volatile semiconductor memory device has a semiconductor layer having a pair of source/drain regions formed at a predetermined distance and a channel region between the pair of source/drain regions; a first insulating film formed above the semiconductor layer; a charge accumulating film formed above the first insulating film; a second insulating film formed above the charge accumulating film; and a control gate electrode film formed above the second insulating film. The first insulating film includes a first oxide film, a first silicon nitride film formed above the first oxide film and including Boron, and a second oxide film formed above the first silicon nitride film.Type: ApplicationFiled: September 21, 2010Publication date: March 31, 2011Inventors: Akiko SEKIHARA, Tesuya Kai, Masaaki Higuchi, Yoshio Ozawa
-
Patent number: 7679127Abstract: A semiconductor device including a semiconductor substrate; a first gate insulating film formed on the semiconductor substrate; a first gate electrode layer formed on the first gate insulating film; an element isolation insulating film formed so as to isolate a plurality of the first gate electrode layers; a second gate insulating film layer formed so as to cover upper surfaces of the plurality of first gate electrode layers and the element isolation insulating films; and a second gate electrode layer formed on the second gate insulating film layer; and the second gate insulating film layer includes a NONON stacked film structure and a nitride film layer contacting the first gate electrode layer and constituting a lowermost layer of the NONON stack film structure is separated at a portion interposing the plurality of neighboring first gate electrode layers.Type: GrantFiled: June 27, 2007Date of Patent: March 16, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Junichi Shiozawa, Takeo Furuhata, Akiko Sekihara
-
Publication number: 20100019312Abstract: A semiconductor device includes a semiconductor region, a tunnel insulating film formed on a surface of the semiconductor region, a charge-storage insulating film formed on a surface of the tunnel insulating film and containing silicon and nitrogen, a block insulating film formed on a surface of the charge-storage insulating film, and a control gate electrode formed on a surface of the block insulating film, wherein the tunnel insulating film has a first insulating film formed on the surface of the semiconductor region and containing silicon and oxygen, a second insulating film formed on a surface of the first insulating film, and a third insulating film formed on a surface of the second insulating film and containing silicon and oxygen, and a charge trap state in the second insulating film has a lower density than that in the charge-storage insulating film.Type: ApplicationFiled: July 28, 2009Publication date: January 28, 2010Inventors: Katsuyuki SEKINE, Akiko Sekihara, Kensuke Takano, Yoshio Ozawa
-
Publication number: 20080121972Abstract: A semiconductor device including a semiconductor substrate; a first gate insulating film formed on the semiconductor substrate; a first gate electrode layer formed on the first gate insulating film; an element isolation insulating film formed so as to isolate a plurality of the first gate electrode layers; a second gate insulating film layer formed so as to cover upper surfaces of the plurality of first gate electrode layers and the element isolation insulating films; and a second gate electrode layer formed on the second gate insulating film layer; and the second gate insulating film layer includes a NONON stacked film structure and a nitride film layer contacting the first gate electrode layer and constituting a lowermost layer of the NONON stack film structure is separated at a portion interposing the plurality of neighboring first gate electrode layers.Type: ApplicationFiled: June 27, 2007Publication date: May 29, 2008Applicant: Kabushiki Kaisha ToshibaInventors: Junichi Shiozawa, Takeo Furuhata, Akiko Sekihara
-
Patent number: 7126178Abstract: A semiconductor device comprises a semiconductor substrate; a trench formed in the semiconductor substrate or in a layer deposited on the semiconductor substrate; a first conductive layer deposited in the trench and having a recess in the top surface thereof; a buried layer which buries the recess of the first conductive layer and which is made of a material having a melting point lower than that of the first conductive layer; and a second conductive layer formed on the buried layer inside the trench and electrically connected to the first conductive layer.Type: GrantFiled: March 2, 2005Date of Patent: October 24, 2006Assignee: Kabushiki Kaisha ToshibaInventors: Takeo Furuhata, Ichiro Mizushima, Akiko Sekihara, Motoya Kishida, Tsubasa Harada, Takashi Nakao
-
Publication number: 20060097303Abstract: A semiconductor device comprises a semiconductor substrate; a trench formed in the semiconductor substrate or in a layer deposited on the semiconductor substrate; a first conductive layer deposited in the trench and having a recess in the top surface thereof; a buried layer which buries the recess of the first conductive layer and which is made of a material having a melting point lower than that of the first conductive layer; and a second conductive layer formed on the buried layer inside the trench and electrically connected to the first conductive layer.Type: ApplicationFiled: December 21, 2005Publication date: May 11, 2006Inventors: Takeo Furuhata, Ichiro Mizushima, Akiko Sekihara, Motoya Kishida, Tsubasa Harada, Takashi Nakao
-
Patent number: 6982198Abstract: A semiconductor device comprises a semiconductor substrate; a trench formed in the semiconductor substrate or in a layer deposited on the semiconductor substrate; a first conductive layer deposited in the trench and having a recess in the top surface thereof; a buried layer which buries the recess of the first conductive layer and which is made of a material having a melting point lower than that of the first conductive layer; and a second conductive layer formed on the buried layer inside the trench and electrically connected to the first conductive layer.Type: GrantFiled: March 2, 2005Date of Patent: January 3, 2006Assignee: Kabushiki Kaisha ToshibaInventors: Takeo Furuhata, Ichiro Mizushima, Akiko Sekihara, Motoya Kishida, Tsubasa Harada, Takashi Nakao
-
Patent number: 6946699Abstract: A semiconductor device comprises a semiconductor substrate; a trench formed in the semiconductor substrate or in a layer deposited on the semiconductor substrate; a first conductive layer deposited in the trench and having a recess in the top surface thereof; a buried layer which buries the recess of the first conductive layer and which is made of a material having a melting point lower than that of the first conductive layer; and a second conductive layer formed on the buried layer inside the trench and electrically connected to the first conductive layer.Type: GrantFiled: April 10, 2003Date of Patent: September 20, 2005Assignee: Kabushiki Kaisha ToshibaInventors: Takeo Furuhata, Ichiro Mizushima, Akiko Sekihara, Motoya Kishida, Tsubasa Harada, Takashi Nakao
-
Publication number: 20050167720Abstract: A semiconductor device comprises a semiconductor substrate; a trench formed in the semiconductor substrate or in a layer deposited on the semiconductor substrate; a first conductive layer deposited in the trench and having a recess in the top surface thereof; a buried layer which buries the recess of the first conductive layer and which is made of a material having a melting point lower than that of the first conductive layer; and a second conductive layer formed on the buried layer inside the trench and electrically connected to the first conductive layer.Type: ApplicationFiled: March 2, 2005Publication date: August 4, 2005Applicant: Kabushiki Kaisha ToshibaInventors: Takeo Furuhata, Ichiro Mizushima, Akiko Sekihara, Motoya Kishida, Tsubasa Harada, Takashi Nakao
-
Publication number: 20050170582Abstract: A semiconductor device comprises a semiconductor substrate; a trench formed in the semiconductor substrate or in a layer deposited on the semiconductor substrate; a first conductive layer deposited in the trench and having a recess in the top surface thereof; a buried layer which buries the recess of the first conductive layer and which is made of a material having a melting point lower than that of the first conductive layer; and a second conductive layer formed on the buried layer inside the trench and electrically connected to the first conductive layer.Type: ApplicationFiled: March 2, 2005Publication date: August 4, 2005Applicant: Kabushiki Kaisha ToshibaInventors: Takeo Furuhata, Ichiro Mizushima, Akiko Sekihara, Motoya Kishida, Tsubasa Harada, Takashi Nakao
-
Publication number: 20040106254Abstract: A semiconductor device comprises a semiconductor substrate; a trench formed in the semiconductor substrate or in a layer deposited on the semiconductor substrate; a first conductive layer deposited in the trench and having a recess in the top surface thereof; a buried layer which buries the recess of the first conductive layer and which is made of a material having a melting point lower than that of the first conductive layer; and a second conductive layer formed on the buried layer inside the trench and electrically connected to the first conductive layer.Type: ApplicationFiled: April 10, 2003Publication date: June 3, 2004Inventors: Takeo Furuhata, Ichiro Mizushima, Akiko Sekihara, Motoya Kishida, Tsubasa Harada, Takashi Nakao
-
Patent number: 5951755Abstract: A manufacturing method for manufacturing a semiconductor substrate has first annealing step for annealing silicon single crystal to permit oxygen embryos or oxygen precipitations grown from the oxygen embryos precipitating in a predetermined region and a second annealing step for permitting said oxygen embryos or said oxygen precipitations to contract using a second temperature range higher than the first temperature range, said second temperature range being high enough to contract said oxygen embryos and low enough to prevent redistribution of boron from affecting to device characteristics, to form a denuded zone in said predetermined region at the principal surface. An inspection method for inspecting a semiconductor substrate further has measuring step, subsequent to said first and second annealing steps for measuring the density of oxygen embryos grown into oxygen precipitations among those precipitated in said silicon single crystal.Type: GrantFiled: February 14, 1997Date of Patent: September 14, 1999Assignee: Kabushiki Kaisha ToshibaInventors: Moriya Miyashita, Masanobu Ogino, Tadahide Hoshi, Masanori Numano, Shuichi Samata, Akiko Sekihara, Keiko Akita