Patents by Inventor Akila Subramaniam
Akila Subramaniam has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240111596Abstract: A scheduler of an apparatus exposes an application programming interface (API) usable to specify quality-of-service (QoS) parameters, e.g., latency, throughput, and so forth. An application, for instance, specifies the QoS parameters for a workload to be processed using a hardware compute unit. The QoS parameters are employed by the scheduler as a basis to configure a partition within a hardware compute unit. The partition is configured such that processing resources that are available via the partition to process the workload comply with the specified quality-of-service.Type: ApplicationFiled: September 29, 2022Publication date: April 4, 2024Inventors: Tung Chuen Kwong, King Chiu Tam, Akila Subramaniam
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Publication number: 20240111840Abstract: An electronic device uses a tiling scheme selected from among a set of tiling schemes for processing instances of input data through a neural network. Each of the tiling schemes is associated with a different arrangement of portions into which instances of input data are divided for processing in the neural network. In operation, processing circuitry in the electronic device acquires information about a neural network and properties of the processing circuitry. The processing circuitry then selects a given tiling scheme from among a set of tiling schemes based on the information. The processing circuitry next processes instances of input data in the neural network using the given tiling scheme. Processing each instance of input data in the neural network includes dividing the instance of input data into portions based on the given tiling scheme, separately processing each of the portions in the neural network, and combining the respective outputs to generate an output for the instance of input data.Type: ApplicationFiled: September 30, 2022Publication date: April 4, 2024Inventors: Akila Subramaniam, Ying Liu, Tung Chuen Kwong, Juanjo Noguera
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Publication number: 20240112297Abstract: Methods and devices are provided for processing image data on a sub-frame portion basis using layers of a convolutional neural network. The processing device comprises memory and a processor. The processor is configured to determine, for an input tile of an image, a receptive field via backward propagation and determine a size of the input tile based on the receptive field and an amount of local memory allocated to store data for the input tile. The processor determines whether the amount of local memory allocated to store the data of the input tile and padded data for the receptive field.Type: ApplicationFiled: September 30, 2022Publication date: April 4, 2024Applicants: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Tung Chuen Kwong, Ying Liu, Akila Subramaniam
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Patent number: 10796407Abstract: An electronic device, method, and computer readable medium for foveated storage and processing are provided. The electronic device includes a memory, and a processor coupled to the memory. The processor performs head tracking and eye tracking; generates a foveated image from an original image based on the head tracking and the eye tracking; and stores the foveated image using one of: a tile-based method or a frame-based method.Type: GrantFiled: May 11, 2018Date of Patent: October 6, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Manish Goel, Akila Subramaniam, Hideo Tamama, Jeffrey Tang, Seok-Jun Lee
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Patent number: 10565778Abstract: A method of implementing memory transfers for image warping in an electronic device is described. The method comprises receiving an input tile associated with an image; generating a geometric boundary around pixels of the input tile; and remapping the pixels in the geometric boundary to an output tile. An electronic device and a non-transitory computer readable storage medium for performing the method are also disclosed.Type: GrantFiled: August 22, 2017Date of Patent: February 18, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Manish Goel, Akila Subramaniam, Rahul Rithe, Seok-Jun Lee
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Publication number: 20190347763Abstract: An electronic device, method, and computer readable medium for foveated storage and processing are provided. The electronic device includes a memory, and a processor coupled to the memory. The processor performs head tracking and eye tracking; generates a foveated image from an original image based on the head tracking and the eye tracking; and stores the foveated image using one of: a tile-based method or a frame-based method.Type: ApplicationFiled: May 11, 2018Publication date: November 14, 2019Inventors: Manish Goel, Akila Subramaniam, Hideo Tamama, Jeffrey Tang, Seok-Jun Lee
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Publication number: 20190066358Abstract: A method of implementing memory transfers for image warping in an electronic device is described. The method comprises receiving an input tile associated with an image; generating a geometric boundary around pixels of the input tile; and remapping the pixels in the geometric boundary to an output tile. An electronic device and a non-transitory computer readable storage medium for performing the method are also disclosed.Type: ApplicationFiled: August 22, 2017Publication date: February 28, 2019Applicant: Samsung Electronics Co., Ltd.Inventors: Manish Goel, Akila Subramaniam, Rahul Rithe, Seok-Jun Lee
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Patent number: 10034026Abstract: A method of enabling processing of a video stream is described. The method comprises establishing a slice width for frames of the video stream; receiving the video stream; dividing, for each frame of the video stream, the frame into vertical slices having the slice width; storing a frame of the video stream in a re-ordered slice based format. Computer-readable storage medium and a device for enabling processing of a video stream are also described.Type: GrantFiled: April 22, 2016Date of Patent: July 24, 2018Inventors: Akila Subramaniam, Manish Goel, Hamid Rahim Sheikh
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Publication number: 20170309306Abstract: A method of enabling processing of a video stream is described. The method comprises establishing a slice width for frames of the video stream; receiving the video stream; dividing, for each frame of the video stream, the frame into vertical slices having the slice width; storing a frame of the video stream in a re-ordered slice based format.Type: ApplicationFiled: April 22, 2016Publication date: October 26, 2017Applicant: Samsung Electronics Co., Ltd.Inventors: Akila Subramaniam, Manish Goel, Hamid Rahim Sheikh
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Patent number: 9015376Abstract: A low overhead method to handle inter process and peer to peer communication. A queue manager is used to create a list of messages with minimal configuration overhead. A hardware queue can be connected to another software task owned by the same core or a different processor core, or connected to a hardware DMA peripheral. There is no limitation on how many messages can be queued between the producer and consumer cores. The low latency interrupt generation to the processor cores is handled by an accumulator inside the QMSS which can be configured to generate interrupts based on a programmable threshold of descriptors in a queue. The accumulator thus removes the polling overhead from software and boosts performance by doing the descriptor pops and message transfer in the background.Type: GrantFiled: April 29, 2012Date of Patent: April 21, 2015Assignee: Texas Instruments IncorporatedInventors: Michael A. Denio, Brian Karguth, Akila Subramaniam, Charles Fuoco
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Patent number: 8706937Abstract: A bus monitoring and debugging system operating independently without impacting the normal operation of the CPU and without adding any overhead to the application being monitored. Users are alerted to timing problems as they occur, and bus statistics that are relevant to providing insight to system operation are automatically captured. Logging of relevant events may be enabled or disabled when a sliding time window expires, or alternatively by external trigger events.Type: GrantFiled: December 17, 2011Date of Patent: April 22, 2014Assignee: Texas Instruments IncorporatedInventors: Brian Cruickshank, David Quintin Bell, Samuel Paul Visalli, Chunhua Hu, Akila Subramaniam, Charles Fuoco
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Publication number: 20130290984Abstract: A low overhead method to handle inter process and peer to peer communication. A queue manager is used to create a list of messages with minimal configuration overhead. A hardware queue can be connected to another software task owned by the same core or a different processor core, or connected to a hardware DMA peripheral. There is no limitation on how many messages can be queued between the producer and consumer cores. The low latency interrupt generation to the processor cores is handled by an accumulator inside the QMSS which can be configured to generate interrupts based on a programmable threshold of descriptors in a queue. The accumulator thus removes the polling overhead from software and boosts performance by doing the descriptor pops and message transfer in the background.Type: ApplicationFiled: April 29, 2012Publication date: October 31, 2013Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Michael A. Denio, Brian Karguth, Akila Subramaniam, Charles Fuoco
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Publication number: 20130054852Abstract: Transaction requests in an interconnect fabric in a system with multiple nodes are managed in a manner that prevents deadlocks. One or more patterns of transaction requests from a master device to various slave devices within the multiple nodes that may cause a deadlock are determined. While the system is in operation, an occurrence of one of the patterns is detected by observing a sequence of transaction requests from the master device. A transaction request in the detected pattern is stalled to allow an earlier transaction request to complete in order to prevent a deadlock.Type: ApplicationFiled: August 24, 2011Publication date: February 28, 2013Inventors: Charles Fuoco, Akila Subramaniam
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Publication number: 20120226839Abstract: A bus monitoring and debugging system operating independently without impacting the normal operation of the CPU and without adding any overhead to the application being monitored. Bus transactions to a selected slave are monitored to determine possible conflicts when multiple masters may be addressing the slave. Users are alerted to timing problems as they occur, and bus statistics that are relevant to providing insight to system operation are automatically captured. Logging of relevant events may be enabled or disabled when a sliding time window expires, by a selected address range or alternatively by external trigger events.Type: ApplicationFiled: January 11, 2012Publication date: September 6, 2012Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Charles Fuoco, Brian Cruickshank, Akila Subramaniam, Chunhua Hu, Samuel Paul Visalli
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Publication number: 20120226837Abstract: A bus monitoring and debugging system operating independently without impacting the normal operation of the CPU and without adding any overhead to the application being monitored. Users are alerted to timing problems as they occur, and bus statistics that are relevant to providing insight to system operation are automatically captured. Logging of relevant events may be enabled or disabled when a sliding time window expires, or alternatively by external trigger events.Type: ApplicationFiled: December 17, 2011Publication date: September 6, 2012Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Brian Cruickshank, David Quintin Bell, Samuel Paul Visalli, Chunhua Hu, Akila Subramaniam, Charles Fuoco
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Patent number: 8171186Abstract: A method for performing write transactions in an interconnect fabric is described. A burst write transaction is received by a bridge coupled to a master. The burst transaction is initiated by a command phase that includes a wait state attribute. The bridge is also coupled to a second bus that is coupled to a slave destination device or to another bridge. The bridge may initiate a cut-through transaction to the second bus when the wait state attribute indicates a master inserted wait state will not be incurred during the burst transaction.Type: GrantFiled: January 31, 2011Date of Patent: May 1, 2012Assignee: Texas Instruments IncorporatedInventors: Brian Jason Karguth, Denis Roland Beaudoin, Akila Subramaniam
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Patent number: 7532646Abstract: A channel-alignment circuit has a controller and a plurality of channel-alignment blocks. Each channel-alignment block synchronizes two or more channels. The controller coordinates the synchronization of channels by the blocks such that (i) channels in each of one or more groups of two or more blocks are synchronized, and (ii) each group of blocks is synchronized independently of any other group.Type: GrantFiled: February 23, 2005Date of Patent: May 12, 2009Assignee: Lattice Semiconductor CorporationInventors: Wai-Bor Leung, Barry Britton, Akila Subramaniam
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Publication number: 20060187966Abstract: A channel-alignment circuit has a controller and a plurality of channel-alignment blocks. Each channel-alignment block synchronizes two or more channels. The controller coordinates the synchronization of channels by the blocks such that (i) channels in each of one or more groups of two or more blocks are synchronized, and (ii) each group of blocks is synchronized independently of any other group.Type: ApplicationFiled: February 23, 2005Publication date: August 24, 2006Inventors: Wai-Bor Leung, Barry Britton, Akila Subramaniam