Abstract: A non-volatile semiconductor memory device includes a memory cell configured to allow electrical writing and erasing, a bit line configured to transmit a potential corresponding to data stored in the memory cell in a column direction, a sense amplifier circuit configured to detect a potential of the bit line, and a bit line coupling circuit coupled between the bit line and the sense amplifier circuit. The bit line coupling circuit includes a first bit line coupling transistor in an outer layout area of the bit line coupling circuit and a second bit line coupling transistor in an inner layout area of the bit line coupling circuit. The first bit line coupling transistor has a longer distance in a channel length direction or in a channel width direction between an impurity diffused layer coupled to the bit line and an element isolation area than the second bit line coupling transistor.

Abstract: A non-volatile semiconductor memory device includes a memory cell configured to allow electrical writing and erasing, a bit line configured to transmit a potential corresponding to data stored in the memory cell in a column direction, a sense amplifier circuit configured to detect a potential of the bit line, and a bit line coupling circuit coupled between the bit line and the sense amplifier circuit. The bit line coupling circuit includes a first bit line coupling transistor in an outer layout area of the bit line coupling circuit and a second bit line coupling transistor in an inner layout area of the bit line coupling circuit. The first bit line coupling transistor has a longer distance in a channel length direction or in a channel width direction between an impurity diffused layer coupled to the bit line and an element isolation area than the second bit line coupling transistor.

Abstract: A nonvolatile semiconductor storage device including memory-cell transistors located in a memory-cell region, each of the transistors including a gate insulating film formed on a semiconductor substrate and a memory-cell gate electrode including a first semiconductor film, an insulating film, and a conductive film; word lines each interconnecting the conductive film of the transistors aligned in a first direction and each including a hook-up portion located in a hook-up region located outside the memory-cell region; and an interlayer insulating film disposed on the upper surface of the memory-cell gate electrodes so as to form a gap between the memory-cell gate electrodes; wherein a second semiconductor film and a first insulating film are disposed in the hook-up region, wherein the interlayer insulating film covers an upper surface of the first insulating film and an upper surface of the plurality of word lines in the hook-up portion.

Abstract: According to one embodiment, memory includes a memory cell transistor including a floating gate electrode, a control gate electrode and a first inter-gate insulating film between floating gate and control gate electrodes, a field effect transistor including a lower electrode layer, an upper electrode layer, and a second inter-gate insulating film between the lower and upper electrode layers. The lower electrode layer having an n-type silicon film, the second inter-gate insulating film having a first opening, and the upper electrode layer having a p-type silicon film. The p-type silicon film is provided on the n-type silicon film via the first opening.