Abstract: A clock switching circuit in which one clock signal is selected from 2N-phase input clock signals with the same frequency but with each shifted in phase (where N is an integer equal to or greater than 3), based on N-bit selection signals, and is output as an output clock signal, comprises a selector group having 2N?1 selectors each of which select and output one clock signal from two input clock signals, and an operation control circuit which generates 2N?1 operation control signals to execute control to set the 2N?1 selectors into an active state or into a sleep state. The selectors select the clock signals based on the selection signals. The operation control circuit executes control to set a portion of the selectors among the 2N?1 selectors to the active state and to set the remaining selectors to the sleep state, based on the selection signals.

Abstract: A clock switching circuit in which one clock signal is selected from 2N-phase input clock signals with the same frequency but with each shifted in phase (where N is an integer equal to or greater than 3), based on N-bit selection signals, and is output as an output clock signal, comprises a selector group having 2N?1 selectors each of which select and output one clock signal from two input clock signals, and an operation control circuit which generates 2N?1 operation control signals to execute control to set the 2N?1 selectors into an active state or into a sleep state. The selectors select the clock signals based on the selection signals. The operation control circuit executes control to set a portion of the selectors among the 2N?1 selectors to the active state and to set the remaining selectors to the sleep state, based on the selection signals.

Abstract: A clock switching circuit suitably adapted to stable switching operation of high-frequency multiphase clock signals. The clock switching circuit receives two clock signals and selectively outputs one of the two clock signals in accordance with a selection signal. The clock switching circuit includes a switching controller that transfers the selection signal at the beginning of a period in which both of the two clock signals are active, and an internal selector that selectively outputs one of the two clock signals in response to the selection signal transferred from the switching controller.

Abstract: A clock switching circuit suitably adapted to stable switching operation of high-frequency multiphase clock signals. The clock switching circuit receives two clock signals and selectively outputs one of the two clock signals in accordance with a selection signal. The clock switching circuit includes a switching controller that transfers the selection signal at the beginning of a period in which both of the two clock signals are active, and an internal selector that selectively outputs one of the two clock signals in response to the selection signal transferred from the switching controller.

Abstract: A semiconductor device test circuit that prevents unnecessary data from being inputted to a functional macro circuit at the time of testing the functional macro circuit. In a plurality of flip-flops connected in series, serial test pattern data latched by a flip-flop at a stage is latched by a flip-flop at the next stage in synchronization with a first clock signal. The test pattern data latched by flip-flops at all the stages is outputted to the functional macro circuit at once in synchronization with a second clock signal inputted to the flip-flops.