Abstract: A semiconductor integrated circuit includes a flip-flop circuit group having flip-flop circuits of n rows.times.m columns, a row-direction pseudo-random number generator or row- and column-direction pseudo-random number generators, and a logic circuit block, wherein pseudo-random number data can be set in an internal logic circuit which is divided into blocks in a short period of time with a simple circuit construction and with a slight increase in the number of input and output pins and thus the test for the logic circuit block can be simplified.

Abstract: A semiconductor integrated circuit device suitable for an internal logic diagnostic test includes an input terminal pin for receiving data including test data, and an output terminal pin for generating data including operation result data of the device. An internal logic circuit of the device is divided into internal logic units. Scanning flip-flop circuits are arranged between these internal logic units. The scanning flip-flop circuits includes a first plurality of flip-flop circuits arranged along a first scanning direction between the input and output terminals, and a second plurality of flip-flop circuits branched off from each of the first flip-flop circuits and arranged along a second scanning direction. The first flip-flop circuits are preferably constituted by 2-input/2-output flip-flop circuits series-connected along the first scanning direction.