Abstract: A method for forming vias, interconnecting selected wiring layers of an integrated circuit device, which overcomes oxide formation on the wiring metal surface which is exposed at the etched via bottom before filling the via with interconnecting metal. The method first etches the vias through the insulating layer, with a step or stair like wall formation, to expose the underlying metal surface. The exposed metal surface is then sputter etched to remove the undesired oxide layer which forms on the metal surface at the via bottom after being exposed by the etch through process. During the sputter etch oxide removal process, the stair like via wall prevents re-oxidation of the exposed metal surface by stray silicon oxide particles dislodged from the via wall during the sputter process.