Abstract: A solar cell assembly includes a plurality of solar cells and an inter-cell region provided between adjacent ones of the solar cells included in the plurality of solar cells. Each of the solar cells and the inter-cell region includes: a semiconductor substrate having a first conductivity type and having a first main surface and a second main surface that face away from each other; a first amorphous semiconductor layer having a second conductivity type and being provided on a first main surface side of the semiconductor substrate; an insulating layer provided on part of the first amorphous semiconductor layer; and a first transparent conductive film provided on the first amorphous semiconductor layer so as to cover the insulating layer. In a plan view of the solar cell assembly, the insulating layer is provided along the inter-cell region and partially overlapping the inter-cell region.

Abstract: A solar cell assembly includes a plurality of solar cells and an inter-cell region provided between adjacent ones of the solar cells included in the plurality of solar cells. Each of the solar cells and the inter-cell region includes: a semiconductor substrate having a first conductivity type and having a first main surface and a second main surface that face away from each other; a first amorphous semiconductor layer having a second conductivity type and being provided on a first main surface side of the semiconductor substrate; an insulating layer provided on part of the first amorphous semiconductor layer; and a first transparent conductive film provided on the first amorphous semiconductor layer so as to cover the insulating layer. In a plan view of the solar cell assembly, the insulating layer is provided along the inter-cell region and partially overlapping the inter-cell region.

Abstract: There is provided a solar cell manufacturing method comprising: a step of preparing a photoelectric conversion cell having a first main surface and a second main surface; a step of forming a first collector electrode on the first main surface and forming a second collector electrode on the second main surface; a step of measuring characteristic values of the photoelectric conversion cell having the first collector electrode and the second collector electrode thereon; and a step of forming a third collector electrode on at least one of the first main surface and the second main surface based on the characteristic values.

Abstract: This method of manufacturing a solar cell includes a step of forming a photoelectric conversion layer on a substrate with a plasma treatment apparatus including a first electrode provided in a treatment chamber, a second electrode and a gas supply source supplying gas into the treatment chamber. A recess portion having a bottom portion in the form of a curved surface is provided on another surface of the first electrode, while a plurality of through-holes are provided on the bottom portion of the recess portion.

Abstract: In a semiconductor substrate having a first well of a conductivity type opposite to that of the semiconductor substrate, formed on part of a main surface of the semiconductor substrate, a second well of the same conductivity type as the semiconductor substrate, formed on part of a surface region of the first well shallower than the first well, and a third well of a conductivity type opposite to that of the semiconductor substrate, formed in a surface region of the first well, in a region where the second well is not formed and shallower than the first well, by having a fourth well, formed in a region of the main surface of the semiconductor substrate where the first well is not formed and doped with impurities of the same conductivity type as the semiconductor substrate at a lower concentration than the third well, and controlling a reference voltage to be low, it is possible suppress the occurrence of a latch up phenomenon.

Abstract: This method of manufacturing a solar cell includes a step of forming a photoelectric conversion layer on a substrate with a plasma treatment apparatus including a first electrode provided in a treatment chamber, a second electrode and a gas supply source supplying gas into the treatment chamber. A recess portion having a bottom portion in the form of a curved surface is provided on another surface of the first electrode, while a plurality of through-holes are provided on the bottom portion of the recess portion.

Abstract: A capacitor having low voltage dependency and high pn junction diode reverse breakdown voltage. A first n-well is formed in the surface of a p-type silicon substrate. A second n-well is superimposed and formed in the first n-well. A gate electrode is formed along the entire surface of the gate insulation film and part of the field insulation film. A p+ type diffusion layer having a high p-type impurity concentration is formed on the surface of the second n-well. The edge of the p+ diffusion layer is spaced from the boundary between the gate insulation film and the field insulation film at which an electric field concentrates.

Abstract: A semiconductor device including a source region and a drain region spaced from each other by a predetermined interval and formed on a main surface of a semiconductor substrate. A gate electrode is formed on the semiconductor substrate. A trench is filled with insulation material and formed in the main surface of the semiconductor substrate between a location under the gate electrode and at least one of the source region and the drain region with a predetermined depth. An LDD is formed along the trench and has an impurity concentration that is lower than that of the source region and the drain region.

Abstract: In a semiconductor substrate having a first well of a conductivity type opposite to that of the semiconductor substrate, formed on part of a main surface of the semiconductor substrate, a second well of the same conductivity type as the semiconductor substrate, formed on part of a surface region of the first well shallower than the first well, and a third well of a conductivity type opposite to that of the semiconductor substrate, formed in a surface region of the first well, in a region where the second well is not formed and shallower than the first well, by having a fourth well, formed in a region of the main surface of the semiconductor substrate where the first well is not formed and doped with impurities of the same conductivity type as the semiconductor substrate at a lower concentration than the third well, and controlling a reference voltage to be low, it is possible suppress the occurrence of a latch up phenomenon.

Abstract: A capacitor having low voltage dependency and high pn junction diode reverse breakdown voltage. A first n-well is formed in the surface of a p-type silicon substrate. A second n-well is superimposed and formed in the first n-well. A gate electrode is formed along the entire surface of the gate insulation film and part of the field insulation film. A p+ type diffusion layer having a high p-type impurity concentration is formed on the surface of the second n-well. The edge of the p+diffusion layer is spaced from the boundary between the gate insulation film and the field insulation film at which an electric field concentrates.

Abstract: A semiconductor device including a source region and a drain region spaced from each other by a predetermined interval and formed on a main surface of a semiconductor substrate. A gate electrode is formed on the semiconductor substrate. A trench is filled with insulation material and formed in the main surface of the semiconductor substrate between a location under the gate electrode and at least one of the source region and the drain region with a predetermined depth. An LDD is formed along the trench and has an impurity concentration that is lower than that of the source region and the drain region.