Patents by Inventor Akinari Kida
Akinari Kida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 6492203Abstract: A semiconductor device fabrication process comprising an encapsulation step of carrying out encapsulation by vacuum pressure differential printing by the use of a liquid resin encapsulant containing a solvent in an amount of from 5% by weight to 50% by weight, and preferably from 25% by weight to 50% by weight. The encapsulation step comprises: printing the liquid resin encapsulant by vacuum pressure differential printing in such a way that; the encapsulant covers at least an internal connecting terminal provided on a substrate, a semiconductor chip, and a wire interconnecting the internal connecting terminal and the semiconductor chip; and that the thickness of the encapsulant lying above the wire at the highest position of the wire comes to be at least 0.8 times the thickness of the encapsulant lying beneath the wire at the same position; and curing or drying the encapsulant.Type: GrantFiled: October 5, 2000Date of Patent: December 10, 2002Assignee: Hitachi Chemical Company, Ltd.Inventors: Yoshiaki Wakashima, Naoki Fukutomi, Kazuhisa Suzuki, Toshio Yamazaki, Tsutomu Kitakatsu, Susumu Naoyuki, Akinari Kida
-
Patent number: 6268648Abstract: A semiconductor device comprising a substrate with a cavity portion for mounting a semiconductor chip is provided to achieve a high reliability and to decrease a size and a fabricating cost. The cavity portion capable of mounting the semiconductor chip (1) at the center portion of the substrate is formed by press forming with a projected portion (13a) of a die (13) while adhering a press shapeable wiring body comprising a copper wiring (12) which becomes wiring material, a barrier layer (11) such as nickel alloy or the like, and a copper foil (10) which is a carrier layer, to a plastic substrate (14,15), so as to have wiring (2) buried into a surface of the substrate and to form a ramp between an inner connection terminal portion connecting to the semiconductor chip (1) and an external connection terminal portion connecting to an external connection terminals (5), the internal and external connection terminal portions being two edge portions of the wiring (2).Type: GrantFiled: October 29, 1999Date of Patent: July 31, 2001Assignee: Hitachi Chemical Co., Ltd.Inventors: Naoki Fukutomi, Yoshiaki Wakashima, Susumu Naoyuki, Akinari Kida
-
Patent number: 5885723Abstract: Provided is bonding film for printed circuit boards which is resistant to cracking even when bent with a small radius of curvature, has a sufficient mechanical strength even in its semi-cured state so that the handling may be facilitated, is not undesirably brittle and therefore does not produce undesired debris when cut, and is flexible and flame retardant at the same time. The bonding film may consist of (i) high polymer epoxy resin; (ii) denatured polyamide obtained by reacting epoxy resin and polyamide; (iii) polyfunctional epoxy resin; and (iv) curing agent. Preferably, the denatured polyamide includes a polyalkylene-glycol residue or a polycarbonate-diol residue. Preferably, the high polymer epoxy resin is produced by the polymerization of bifunctional epoxy resin and bifunctional phenol resin, and has a weight averaged molecular weight equal to 50,000 or higher.Type: GrantFiled: December 19, 1997Date of Patent: March 23, 1999Assignee: Hitachi Chemical Company, Ltd.Inventors: Atsushi Takahashi, Shinji Ogi, Koji Morita, Kazunori Yamamoto, Ken Nanaumi, Kiyoshi Hirosawa, Akinari Kida, Takao Hirayama, Toshihiko Ito, Hiroaki Hirakura
-
Patent number: 5690837Abstract: In a process for producing a multilayer printed circuit board comprising drilling holes for via holes in a composite film material containing at least a copper foil and an insulating half-cured adhesive layer, laminating the resulting film material on an innerlayer circuit substrate, ad electrically connecting an innerlayer circuit with an outer layer copper foil, when an adhesive resin flowed into the holes is roughened, or when a composite film material having a copper foil of less than 12 .mu.m thick formed on a carrier is used, or a special cushion material is further laminated on the laminate of the innerlayer circuit substrate and the film material, electrical connection reliability is enhanced and circuit density can be increased with easy steps.Type: GrantFiled: December 21, 1995Date of Patent: November 25, 1997Assignee: Hitachi Chemical Company, Ltd.Inventors: Akishi Nakaso, Koichi Tsuyama, Kazuhisa Otsuka, Haruo Ogino, Yoshihiro Tamura, Teiichi Inada, Kazunori Yamamoto, Akinari Kida, Atsushi Takahashi, Yoshiyuki Tsuru, Shigeharu Arike
-
Patent number: 5689879Abstract: A metal foil for printed wiring boards comprising a first copper layer to be adhered to a resin, a second copper layer having a sufficient strength as a metal layer and a nickel-phosphorus alloy layer containing 1.1% by weight or more of phosphorus formed between the first and second copper layers is suitable for producing printed wiring boards having excellent heat resistance, particularly during production procedures.Type: GrantFiled: December 16, 1994Date of Patent: November 25, 1997Assignee: Hitachi Chemical Company, Ltd.Inventors: Naoyuki Urasaki, Kouichi Tsuyama, Kiyoshi Hasegawa, Shuichi Hatakeyama, Akinari Kida, Akishi Nakaso, Hiroshi Nomura
-
Patent number: 5638598Abstract: A process for producing a wiring board involves laminating a metal foil on both sides of an insulating substrate not completely cured, followed by pressing with heating; drilling holes in the resulting laminate for connecting circuits therein; removing portions of the metal foils in narrow areas around the holes to form hollow portions in the metal foils; and filling a flowable electroconductive substance in the holes and the hollow portions.Type: GrantFiled: June 5, 1995Date of Patent: June 17, 1997Assignee: Hitachi Chemical Company, Ltd.Inventors: Akishi Nakaso, Kouichi Tsuyama, Akinari Kida, Shuichi Hatakeyama, Naoyuki Urasaki
-
Patent number: 5444189Abstract: A wiring board comprising one or more inner layer circuit substrates and outer circuit layers formed from metal foil layers on both sides of said dinner layer circuit substrates via prepregs, said inner layer circuit substrate comprising an insulating layer and metal foil layers formed on both sides of said insulating layer, at least one inner layer circuit substrate or said outer circuit layers or both having hollow portions in the metal foil layer filled with an electroconductive substance, said wiring board having one or more through-holes at least in the hollow portions and filled with the electroconductive substance, has high reliability and a high wiring density.Type: GrantFiled: June 17, 1993Date of Patent: August 22, 1995Assignee: Hitachi Chemical Co., Ltd.Inventors: Akishi Nakaso, Kouichi Tsuyama, Akinari Kida, Shuichi Hatakeyama, Naoyuki Urasaki
-
Patent number: 5403672Abstract: A metal foil for printed wiring boards comprising a first copper layer to be adhered to a resin, a second copper layer having a sufficient strength as a metal layer and a nickel-phosphorus alloy layer containing 1.1% by weight or more of phosphorus formed between the first and second copper layers is suitable for producing printed wiring boards having excellent heat resistance, particularly during production procedures.Type: GrantFiled: May 12, 1993Date of Patent: April 4, 1995Assignee: Hitachi Chemical Co., Ltd.Inventors: Naoyuki Urasaki, Kouichi Tsuyama, Kiyoshi Hasegawa, Shuichi Hatakeyama, Akinari Kida, Akishi Nakaso, Hiroshi Nomura
-
Patent number: 4830691Abstract: A wiring board comprising (A) a base substrate on which the necessary wiring pattern has already been formed, and (B) a multi-layer substrate bonded to the wiring pattern side of said base substrate (A) and comprising heat-resistant resin layers and thin-film wiring patterns formed by a thin film forming method under vacuum can mount LSI chips on the substrate and realize increased density of signal wiring.Type: GrantFiled: March 31, 1987Date of Patent: May 16, 1989Assignee: Hitachi Chemical Company, Ltd.Inventors: Akinari Kida, Naoki Fukutomi, Yoshiaki Tsubomatsu, Takuya Yasuoka