Abstract: An instantaneous phase detecting circuit for detecting the phase of a digital phase modulation wave signal which includes first and second logic circuits, first and second phase detecting circuits, and a third logic circuit. The first and second logic circuits receive the modulation wave signal, the first logic circuit receives a first carrier signal, and the second logic circuit receives a second carrier signal, the phase of the second carrier signal being delayed by a fixed period with respect to the phase of the first carrier signal. The first and second logic circuits generate first and second arithmetic outputs which are received by the first and second phase detecting circuits which detect the phases of the first and second arithmetic outputs to generate first and second detection output signals respectively.

Abstract: A clock recovery signal generating circuit for generating a clock recovery signal includes a plurality of detection axis cross detectors varied in magnitude of detection axis admitting a phase difference signal, for detecting the time at which the phase difference signal crosses the detection axis of a prescribed magnitude. A locus sorter discriminates and sorts the locus of a change in the phase difference signal based on the data of timing obtained by the detection axis cross detectors and generates a timing adjusting signal in conformity with the result of the sorting. Timing control generates a clock recovery signal by correcting the data of timing obtained by one of the plurality of detection axis cross detectors designated by the timing adjusting signal with the time designated by the timing adjusting signal.