Patents by Inventor Akinori Funahashi

Akinori Funahashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Switching reduction bus using data bit inversion
    Patent number: 10915487
    Abstract: Apparatus and methods structured with respect to a data bus having a number of data lines and a number of shield lines can be implemented in a variety of applications. Such apparatus and methods can include driver and receiver circuits that operate to generate and/or decode a data bit inversion signal associated with data propagated on data lines of the data bus. The driver and receiver circuits may be arranged to operate on a two bit basis to interface with the data bus having data lines grouped with respect to the two bits with shield lines for the respective two bit data lines.
    Type: Grant
    Filed: August 28, 2019
    Date of Patent: February 9, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Akinori Funahashi, Chikara Kondo
  • Semiconductor layered device with data bus
    Patent number: 10635623
    Abstract: Apparatuses and methods of data communication between semiconductor chips are described. An example apparatus includes: a first die including a first switch circuit that receives a plurality of data signals, and further provides the plurality of data signals to a plurality of corresponding first ports among a plurality of first data ports and a first data redundancy port; and a second die including a second switch circuit that receives the plurality of data signals from the first die at a plurality of corresponding second ports among a plurality of second data ports and a second data redundancy port and further provides the plurality of data signals to a memory array.
    Type: Grant
    Filed: October 3, 2018
    Date of Patent: April 28, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Chikara Kondo, Akinori Funahashi
  • SWITCHING REDUCTION BUS USING DATA BIT INVERSION WITH SHIELD LINES
    Publication number: 20190384739
    Abstract: Apparatus and methods structured with respect to a data bus having a number of data lines and a number of shield lines can be implemented in a variety of applications. Such apparatus and methods can include driver and receiver circuits that operate to generate and/or decode a data bit inversion signal associated with data propagated on data lines of the data bus. The driver and receiver circuits may be arranged to operate on a two bit basis to interface with the data bus having data lines grouped with respect to the two bits with shield lines for the respective two bit data lines. Additional apparatus and methods are disclosed.
    Type: Application
    Filed: August 28, 2019
    Publication date: December 19, 2019
    Inventors: Akinori Funahashi, Chikara Kondo
  • Switching reduction bus using data bit inversion with shield lines
    Patent number: 10459871
    Abstract: Apparatus and methods structured with respect to a data bus having a number of data lines and a number of shield lines can be implemented in a variety of applications. Such apparatus and methods can include driver and receiver circuits that operate to generate and/or decode a data bit inversion signal associated with data propagated on data lines of the data bus. The driver and receiver circuits may be arranged to operate on a two bit basis to interface with the data bus having data lines grouped with respect to the two bits with shield lines for the respective two bit data lines.
    Type: Grant
    Filed: September 13, 2017
    Date of Patent: October 29, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Akinori Funahashi, Chikara Kondo
  • SWITCHING REDUCTION BUS USING DATA BIT INVERSION WITH SHIELD LINES
    Publication number: 20190079893
    Abstract: Apparatus and methods structured with respect to a data bus having a number of data lines and a number of shield lines can be implemented in a variety of applications. Such apparatus and methods can include driver and receiver circuits that operate to generate and/or decode a data bit inversion signal associated with data propagated on data lines of the data bus. The driver and receiver circuits may be arranged to operate on a two bit basis to interface with the data bus having data lines grouped with respect to the two bits with shield lines for the respective two bit data lines. Additional apparatus and methods are disclosed.
    Type: Application
    Filed: September 13, 2017
    Publication date: March 14, 2019
    Inventors: Akinori Funahashi, Chikara Kondo
  • SEMICONDUCTOR LAYERED DEVICE WITH DATA BUS
    Publication number: 20190034370
    Abstract: Apparatuses and methods of data communication between semiconductor chips are described. An example apparatus includes: a first die including a first switch circuit that receives a plurality of data signals, and further provides the plurality of data signals to a plurality of corresponding first ports among a plurality of first data ports and a first data redundancy port; and a second die including a second switch circuit that receives the plurality of data signals from the first die at a plurality of corresponding second ports among a plurality of second data ports and a second data redundancy port and further provides the plurality of data signals to a memory array.
    Type: Application
    Filed: October 3, 2018
    Publication date: January 31, 2019
    Inventors: Chikara Kondo, Akinori Funahashi
  • Semiconductor layered device with data bus
    Patent number: 10146719
    Abstract: Apparatuses and methods of data communication between semiconductor chips are described. An example apparatus includes: a first die including a first switch circuit that receives a plurality of data signals, and further provides the plurality of data signals to a plurality of corresponding first ports among a plurality of first data ports and a first data redundancy port; and a second die including a second switch circuit that receives the plurality of data signals from the first die at a plurality of corresponding second ports among a plurality of second data ports and a second data redundancy port and further provides the plurality of data signals to a memory array.
    Type: Grant
    Filed: March 24, 2017
    Date of Patent: December 4, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Chikara Kondo, Akinori Funahashi
  • SEMICONDUCTOR LAYERED DEVICE WITH DATA BUS
    Publication number: 20180277175
    Abstract: Apparatuses and methods of data communication between semiconductor chips are described. An example apparatus includes: a first die including a first switch circuit that receives a plurality of data signals, and further provides the plurality of data signals to a plurality of corresponding first ports among a plurality of first data ports and a first data redundancy port; and a second die including a second switch circuit that receives the plurality of data signals from the first die at a plurality of corresponding second ports among a plurality of second data ports and a second data redundancy port and further provides the plurality of data signals to a memory array.
    Type: Application
    Filed: March 24, 2017
    Publication date: September 27, 2018
    Applicant: Micron Technology, Inc.
    Inventors: Chikara Kondo, Akinori Funahashi