Abstract: When a peripheral control processor is put, in a data processing system, into a down state from a normal state of operation upon occurrence of a failure, a failure recovery informing arrangement comprises a failure occurrence signal producing circuit for delivering a failure occurrence signal to a diagnostic bus. Detecting the failure occurrence signal, a detecting circuit delivers a detection signal to a system bus. Responsive to the detection signal, a recovery command signal producing circuit delivers a recovery command signal back to the system bus rather than, through a specific hardware line, directly to the peripheral control processor. Instead of the specific hardware line, a processing circuit is used in processing the recovery command signal into a peripheral initializing signal and a recovery informing signal to supply them to the peripheral control processor through the diagnostic bus. The initializing signal is for turning the down state to the normal state.

Abstract: In order to ensure that separately arranged instruction processing and execution units do not use the same bus and the same time, and to eliminate the need for a multiplexer, when the execution unit requires the use of the bus, a pause signal is fed to the instruction processing unit to temporarily disable a processing portion involved therein in case the both units use the same bus concurrently.