Patents by Inventor Akinori KANETAKE

Akinori KANETAKE has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11264491
    Abstract: Provided is a semiconductor device including a semiconductor substrate provided with a transistor portion, wherein the semiconductor substrate includes, in the transistor portion, a drift region of a first conductivity type; an accumulation region of the first conductivity type that has a higher doping concentration than the drift region; a collector region of a second conductivity type; and a plurality of gate trench portions and a plurality of dummy trench portions that are provided extending in a predetermined extension direction in the top surface of the semiconductor substrate, and are arranged in an arrangement direction orthogonal to the extension direction, and the transistor portion includes a first region that includes a gate trench portion; and a second region in which the number of dummy trench portions arranged in a unit length in the arrangement direction is greater than in the first region.
    Type: Grant
    Filed: July 28, 2020
    Date of Patent: March 1, 2022
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Daisuke Ozaki, Akinori Kanetake, Tohru Shirakawa, Yosuke Sakurai
  • Patent number: 11139291
    Abstract: A semiconductor device is provided, including a semiconductor substrate, wherein the semiconductor substrate has: a diode region; a transistor region; and a boundary region that is positioned between the diode region and the transistor region, the boundary region includes a defect region that is provided: at a predetermined depth position on a front surface-side of the semiconductor substrate; and to extend from an end portion of the boundary region adjacent to the diode region toward the transistor region, at least part of the boundary region does not include a first conductivity-type emitter region exposed on a front surface of the semiconductor substrate, and the transistor region does not have the defect region below a mesa portion that is sandwiched by two adjacent trench portions, and closest to the boundary region among the mesa portions having the emitter region.
    Type: Grant
    Filed: November 29, 2019
    Date of Patent: October 5, 2021
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Takahiro Tamura, Yuichi Onozawa, Misaki Takahashi, Kaname Mitsuzuka, Daisuke Ozaki, Akinori Kanetake
  • Publication number: 20200357904
    Abstract: Provided is a semiconductor device including a semiconductor substrate provided with a transistor portion, wherein the semiconductor substrate includes, in the transistor portion, a drift region of a first conductivity type; an accumulation region of the first conductivity type that has a higher doping concentration than the drift region; a collector region of a second conductivity type; and a plurality of gate trench portions and a plurality of dummy trench portions that are provided extending in a predetermined extension direction in the top surface of the semiconductor substrate, and are arranged in an arrangement direction orthogonal to the extension direction, and the transistor portion includes a first region that includes a gate trench portion; and a second region in which the number of dummy trench portions arranged in a unit length in the arrangement direction is greater than in the first region.
    Type: Application
    Filed: July 28, 2020
    Publication date: November 12, 2020
    Inventors: Daisuke OZAKI, Akinori KANETAKE, Tohru SHIRAKAWA, Yosuke SAKURAI
  • Patent number: 10622350
    Abstract: Provided is a semiconductor device including transistor regions and diode regions each extending from a given one edge of an active region to a different edge of the active region, a first-conductivity-type pad well region in contact with a gate runner region shaped like a rectangular ring and provided within the gate runner region, and first-conductivity-type collector regions provided in the transistor regions in a one-to-one correspondence and second-conductivity-type cathode regions provided in the diode regions in a one-to-one correspondence. Here, an edge of the pad well region at which the pad well region ends in an arranging direction extends in an extending direction, and the arranging direction is orthogonal to the extending direction in which the transistor regions and the diode regions extend, and any one or more of the collector regions are positioned below the edge of the pad well region.
    Type: Grant
    Filed: December 6, 2018
    Date of Patent: April 14, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Akinori Kanetake, Misaki Takahashi
  • Publication number: 20200098747
    Abstract: A semiconductor device is provided, including a semiconductor substrate, wherein the semiconductor substrate has: a diode region; a transistor region; and a boundary region that is positioned between the diode region and the transistor region, the boundary region includes a defect region that is provided: at a predetermined depth position on a front surface-side of the semiconductor substrate; and to extend from an end portion of the boundary region adjacent to the diode region toward the transistor region, at least part of the boundary region does not include a first conductivity-type emitter region exposed on a front surface of the semiconductor substrate, and the transistor region does not have the defect region below a mesa portion that is sandwiched by two adjacent trench portions, and closest to the boundary region among the mesa portions having the emitter region.
    Type: Application
    Filed: November 29, 2019
    Publication date: March 26, 2020
    Inventors: Takahiro TAMURA, Yuichi ONOZAWA, Misaki TAKAHASHI, Kaname MITSUZUKA, Daisuke OZAKI, Akinori KANETAKE
  • Publication number: 20190252374
    Abstract: Provided is a semiconductor device including transistor regions and diode regions each extending from a given one edge of an active region to a different edge of the active region, a first-conductivity-type pad well region in contact with a gate runner region shaped like a rectangular ring and provided within the gate runner region, and first-conductivity-type collector regions provided in the transistor regions in a one-to-one correspondence and second-conductivity-type cathode regions provided in the diode regions in a one-to-one correspondence. Here, an edge of the pad well region at which the pad well region ends in an arranging direction extends in an extending direction, and the arranging direction is orthogonal to the extending direction in which the transistor regions and the diode regions extend, and any one or more of the collector regions are positioned below the edge of the pad well region.
    Type: Application
    Filed: December 6, 2018
    Publication date: August 15, 2019
    Inventors: Akinori KANETAKE, Misaki TAKAHASHI